feat(trap): *tval captures inst on II & VI in XiangShan (#29) · OpenXiangShan/riscv-isa-sim@4dba2bc

Triggered via push August 30, 2024 14:26

cebarobot

difftest

Status Success

Total duration 5m 28s

Artifacts 3

build-difftest-so.yml

on: push

Matrix: Build spike-so for difftest

Produced during runtime

Name	Size
riscv64-nutshell-spike-so Expired	1.95 MB
riscv64-rocket_chip-spike-so Expired	1.95 MB
riscv64-xiangshan-spike-so Expired	1.95 MB