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fix(csr): htinst/mtinst are always written 0 when trap in XiangShan #23

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fix(csr): htinst/mtinst are always written 0 when trap in XiangShan

fix(csr): htinst/mtinst are always written 0 when trap in XiangShan #23

Triggered via push September 10, 2024 09:43
@huxuan0307huxuan0307
pushed 347cd0e
difftest
Status Success
Total duration 6m 6s
Artifacts 3

build-difftest-so.yml

on: push
Matrix: Build spike-so for difftest
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Name Size
riscv64-nutshell-spike-so Expired
1.94 MB
riscv64-rocket_chip-spike-so Expired
1.95 MB
riscv64-xiangshan-spike-so Expired
1.95 MB