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OpenXiangShan / riscv-isa-sim Public

forked from riscv-software-src/riscv-isa-sim

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CI for difftest

feat(Zicclsm): add misalign store check for CPU=XIANGSHAN (#67) #115

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feat(Zicclsm): add misalign store check for CPU=XIANGSHAN (#67)

feat(Zicclsm): add misalign store check for CPU=XIANGSHAN (#67) #115

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1 warning

ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636

Build spike-so for difftest (xiangshan)

Build spike-so for difftest (xiangshan)

succeeded Dec 9, 2024 in 5m 7s

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