fix(rva, trigger): For rva instr, raise BP from trigger prior to misa…

…ligned.
OpenXiangShan · Oct 28, 2024 · 5c63a0e · 5c63a0e
1 parent 6a83d0c
commit 5c63a0e
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Showing 2 changed files with 8 additions and 0 deletions.
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
@@ -309,6 +309,8 @@ void mmu_t::store_slow_path(reg_t original_addr, reg_t len, const uint8_t* bytes
 {
   auto access_info = generate_access_info(original_addr, STORE, xlate_flags);
   reg_t transformed_addr = access_info.transformed_vaddr;
+  check_triggers(triggers::OPERATION_STORE, transformed_addr, access_info.effective_virt);
+
   if (actually_store) {
     reg_t trig_len = len;
     const uint8_t* trig_bytes = bytes;

diff --git a/riscv/mmu.h b/riscv/mmu.h
@@ -179,6 +179,12 @@ class mmu_t
   template<typename T, typename op>
   T amo(reg_t addr, op f) {
     convert_load_traps_to_store_traps({
+
+      xlate_flags_t xlate_flags = {};
+      auto access_info = generate_access_info(addr, LOAD, xlate_flags);
+      reg_t transformed_addr = access_info.transformed_vaddr;
+      check_triggers(triggers::OPERATION_LOAD, transformed_addr, access_info.effective_virt);
+
       store_slow_path(addr, sizeof(T), nullptr, {}, false, true);
       auto lhs = load<T>(addr);
       sim->is_amo = true;