Merge and rebase remote-tracking branch 'upstream/master' into difftest #32

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lewislzh wants to merge 327 commits intodifftestfrom

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Commits on Jun 28, 2024

Merge pull request #1715 from abejgonzalez/fix-interactive-vregs
jerryz123
authored
Merge pull request #1714 from abejgonzalez/fix-interactive-insn
jerryz123
authored

Commits on Jul 2, 2024

Commits on Jul 3, 2024

Merge pull request #1719 from YenHaoChen/pr-encoding
aswaterman
authored

Commits on Jul 4, 2024

Merge pull request #1717 from riscv-software-src/fix-ss-load
aswaterman
authored

Commits on Jul 5, 2024

Commits on Jul 6, 2024

Add Ssdbltrp
ved-rivos
committed

Commits on Jul 8, 2024

Merge pull request #1700 from ved-rivos/ssdbltrp
aswaterman
authored

Commits on Jul 15, 2024

Deprecate dcsr.halt
YenHaoChen
committed

Commits on Jul 16, 2024

zkr: check extension availability in csr_mseccef permssion check

binno
authored and
chihminchao
committed
ssqosid: modify permission check condition for srmcfg

binno
authored and
chihminchao
committed

Commits on Jul 17, 2024

Commits on Jul 18, 2024

Commits on Jul 20, 2024

Merge pull request #1718 from YenHaoChen/pr-pm
aswaterman
authored

Commits on Jul 21, 2024

Merge pull request #1729 from YenHaoChen/pr-require-vector
aswaterman
authored

Commits on Jul 23, 2024

Commits on Jul 25, 2024

Commits on Aug 1, 2024

Commits on Aug 2, 2024

Commits on Aug 5, 2024

Commits on Aug 9, 2024

Commits on Aug 11, 2024

Fix ordering of B single-letter extension
jerryz123
authored

Commits on Aug 12, 2024

Commits on Aug 16, 2024

pointer masking: Fix: Let transformed_addr of fetching be unchanged
YenHaoChen
committed

Commits on Aug 18, 2024

Commits on Aug 19, 2024

Commits on Aug 20, 2024

For mcontrol6, default to BEFORE timing.
rtwfroody
committed

Commits on Aug 26, 2024

pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV in v1.0.0-rc2
YenHaoChen
committed

Commits on Aug 27, 2024

Commits on Aug 29, 2024

pointer masking: Always apply sstatus.MXR regardless of effective V
YenHaoChen
committed

Commits on Aug 30, 2024

Commits on Sep 2, 2024

Merge pull request #1788 from riscv-software-src/support-larger-addresses
aswaterman
authored

Commits on Sep 3, 2024

Commits on Sep 6, 2024

Ignore vscode project files

poemonsense
authored and
lewislzh
committed
Add fuzz harness

poemonsense
authored and
lewislzh
committed
Add test interface to main

poemonsense
authored and
lewislzh
committed
Update Makefile to support libafl

poemonsense
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lewislzh
committed
Makefile: fix dependency on spike generated files

poemonsense
authored and
lewislzh
committed
Disable default signal handlers.

poemonsense
authored and
lewislzh
committed
fuzz: remove catiss dependencies

poemonsense
authored and
lewislzh
committed
fuzz: use macros to switch code blocks

poemonsense
authored and
lewislzh
committed
Rewrite difftest support for Spike as a REF

poemonsense
authored and
lewislzh
committed
csrs: set mstatus.fs to 0 or 3 for CPU_ROCKET_CHIP

poemonsense
authored and
lewislzh
committed
trap: make the tval values on insn_trap configurable

poemonsense
authored and
lewislzh
committed
Add support for an optional flash region

poemonsense
authored and
lewislzh
committed
difftest: fix the memcpy for n > PGSIZE

poemonsense
authored and
lewislzh
committed
mmu: update the physical address for DUTs

poemonsense
authored and
lewislzh
committed
Update ASID configs for different DUTs.

poemonsense
authored and
lewislzh
committed
Update misa write mask for rocket-chip

poemonsense
authored and
lewislzh
committed
Update medeleg write mask for rocket-chip

poemonsense
authored and
lewislzh
committed
Change the default mmu capability to Sv39 for DUTs

poemonsense
authored and
lewislzh
committed
Add support for difftest logs and traces

poemonsense
authored and
lewislzh
committed
Add zicntr extension for rocket-chip

poemonsense
authored and
lewislzh
committed
Move macro definitions to a separated header file

poemonsense
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lewislzh
committed
Add support for disabling AMO store diff

poemonsense
authored and
lewislzh
committed
Set tval to zero on instruction misaligned exceptions

poemonsense
authored and
lewislzh
committed
Fix the missing AMO store condition for SC

poemonsense
authored and
lewislzh
committed
Fix the display for FPR

poemonsense
authored and
lewislzh
committed
mmu: set is_amo before store operations

poemonsense
authored and
lewislzh
committed
difftest: use rom_device_t for the read-only flash

poemonsense
authored and
lewislzh
committed
Add Sdtrig isa string with permission checkers for CSRs

poemonsense
authored and
lewislzh
committed
difftrace: use Enum to wrap memory access types

poemonsense
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lewislzh
committed
Add support for instruction traces

poemonsense
authored and
lewislzh
committed
Add support for forced SC failures

poemonsense
authored and
lewislzh
committed
Add support for REF-provided disambiguation state

poemonsense
authored and
lewislzh
committed
Add support for PTW's ambiguation states

poemonsense
authored and
lewislzh
committed
Add support for ambiguation after satp is updated

poemonsense
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lewislzh
committed
store_tracker: check the next position if needed

poemonsense
authored and
lewislzh
committed
csrs: align the behaviors of epc with rocket-chip

poemonsense
authored and
lewislzh
committed
difftest: fix the memory leak on plugin_devices

poemonsense
authored and
lewislzh
committed
difftest: fix the flash base address

poemonsense
authored and
lewislzh
committed
csr,tvec: mode is non-writable for CPU_NUTSHELL

poemonsense
authored and
lewislzh
committed
proc: fix the counteren_mask for rocket-chip

poemonsense
authored and
lewislzh
committed
mmu: clear sc_failed after check_load_reservation

poemonsense
authored and
lewislzh
committed
difftest: add on_demand option to regcpy

poemonsense
authored and
lewislzh
committed
proc: fix the IALIGN for RVC

poemonsense
authored and
lewislzh
committed
Update marchid for rocket-chip

poemonsense
authored and
lewislzh
committed
Disable time CSR in difftest mode

poemonsense
authored and
lewislzh
committed
csrs: fix the permissions of mcontext

poemonsense
authored and
lewislzh
committed
processor: fix the mimpid for rocket-chip

poemonsense
authored and
lewislzh
committed
sim: disable routine timer update for DiffTest

poemonsense
authored and
lewislzh
committed
Update default CSR values and masks for NutShell

poemonsense
authored and
lewislzh
committed
csrs: mstatus.fs is always zero in NutShell

poemonsense
authored and
lewislzh
committed
Add support for sanitizer coverage instrumentation

poemonsense
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lewislzh
committed
Add the difftest_display interface

poemonsense
authored and
lewislzh
committed
Allow the memory size to be overrided at run-time

poemonsense
authored and
lewislzh
committed
Allow the mhartid to be overrided at run-time

poemonsense
authored and
lewislzh
committed
mmu: change the size of reservation sets for DIFFTEST

poemonsense
authored and
lewislzh
committed
sfence_vma: fix the missing flush_tlb_on_sfence_vma

poemonsense
authored and
lewislzh
committed
difftrace: set satp_written only if vm enabled previously

poemonsense
authored and
lewislzh
committed
decode: disable 48- and 64-bit instructions if needed

poemonsense
authored and
lewislzh
committed
Add support for the ref_skip_one interface

poemonsense
authored and
lewislzh
committed
Update PMP configs for XIANGSHAN

poemonsense
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lewislzh
committed
debug,dummy: return false on out-of-range accesses

poemonsense
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lewislzh
committed
Create README.md

poemonsense
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lewislzh
committed
Update README.md

poemonsense
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lewislzh
committed
proc: avoid initializing PMP entries at reset with DIFFTEST

poemonsense
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lewislzh
committed
Show PMP registers on reg_display

poemonsense
authored and
lewislzh
committed
Update writable mask for `misa` of XiangShan

poemonsense
authored and
lewislzh
committed
Update `mimpid` and `marchid` for XiangShan

poemonsense
authored and
lewislzh
committed
Add support for RISC-V vector extension difftest (#3)

weidingliu
authored and
lewislzh
committed
difftest: fix init of mstatus (#4)

weidingliu
authored and
lewislzh
committed
difftest: fix the constructor of cfg_t

poemonsense
authored and
lewislzh
committed
difftest: fix the plugin_devices

poemonsense
authored and
lewislzh
committed
difftest: avoid double-free of plugin_devices

poemonsense
authored and
lewislzh
committed
difftest: fix unexcepted non-trap when accessing 16-63 PMP CSRs (#12)

cebarobot
authored and
lewislzh
committed
RVH: Support RVH difftest (#11)

authored and
lewislzh
committed
CSR: fix tval for breakpoint exception (#13)

wissygh
authored and
lewislzh
committed
config: rewrite isa string define to allow enable both RVV & RVH (#14)

cebarobot
authored and
lewislzh
committed
config: enable RVH for XiangShan as default (#15)

cebarobot
authored and
lewislzh
committed
store trace: could close store trace (#17)

xyyy1420
authored and
lewislzh
committed
config: fix written error (#16)

xyyy1420
authored and
lewislzh
committed
Enable RVV for XiangShan

poemonsense
authored and
lewislzh
committed
config: add Zicond for Xiangshan (#18)

cyyself
authored and
lewislzh
committed
difftest: update arguments of sim_t constructor

poemonsense
authored and
lewislzh
committed
wfi: treat wfi as nop when difftest (#20)

cebarobot
authored and
lewislzh
committed
fcsr: add fcsr for difftest.

NewPaulWalker
authored and
lewislzh
committed
fcsr: using fcsr instead fflags and frm.

NewPaulWalker
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lewislzh
committed
fcsr: read fcsr from fflags and frm, write fflags amd frm from fcsr.

NewPaulWalker
authored and
lewislzh
committed
fcsr: check fs!=Off before write for fflags/frm, otherwise it will cause abort.

NewPaulWalker
authored and
lewislzh
committed
fcsr: fall back to generate fcsr using fflags and frm.

NewPaulWalker
authored and
lewislzh
committed
fcsr: do not need add mask before write because it will be masked in write.

NewPaulWalker
authored and
lewislzh
committed
fcsr: put fcsr set and get in same CONFIG control with FPR.

NewPaulWalker
authored and
lewislzh
committed
fcsr: fix a spell error.

NewPaulWalker
authored and
lewislzh
committed
fcsr: fix a bug that frm should shift left to generate fcsr.

NewPaulWalker
authored and
lewislzh
committed
isa: define isa string for zicntr and zihpm.

NewPaulWalker
authored and
lewislzh
committed
medeleg: the 3rd bit of medeleg is unwritable when Sdtrig exist.

NewPaulWalker
authored and
lewislzh
committed
sdtrig: support difftest for sdtrig csr except tcontrol.

NewPaulWalker
authored and
lewislzh
committed
sdtrig: trun off sdtrig because it's not fully supported.

NewPaulWalker
authored and
lewislzh
committed
triggers: implement tcontrol

YenHaoChen
authored and
lewislzh
committed
sdtrig: support difftest for tcontrol CSR in sdtrig extension, and turn on sdtrig difftest.

NewPaulWalker
authored and
lewislzh
committed
sdtrig: set the value of tinfo to be consistent with XiangShan and nemu for difftest.

NewPaulWalker
authored and
lewislzh
committed
sdtrig: initialize triggers count when spike as ref.

NewPaulWalker
authored and
lewislzh
committed
csr: define write_raw function for fcsr and vxsat to init difftest, avoid need vs/fs set when set regs.

NewPaulWalker
authored and
lewislzh
committed
ci: add an ci to build spike-so automatically

cebarobot
authored and
lewislzh
committed
config: add config for paddr_bits and mmu_capability (#28)

cebarobot
authored and
lewislzh
committed
feat(trap): *tval captures inst on II & VI in XiangShan (#29)

cebarobot
authored and
lewislzh
committed
config(XIANGSHAN): add sscofpmf, zfa & zfhmin (#30)

cebarobot
authored and
lewislzh
committed
Revert "Lift restriction on physical-address size"
lewislzh
committed