fix(store): make cross-page access consistent with XiangShan behavior

[Anzooooo]

When spike processes a cross-page store, it will be split into two stores and the two stores are independent of each other.
This means that if the store on the lower page can be completed and the store on the upper page triggers a PF exception, the store on the lower page will still be written to memory, and a PF exception will be triggered using the store on the upper page.
For XiangShan, this store instruction can only be completed normally if both stores of the cross-page store can be completed normally.
This modification aligns Spike with XiangShan in the case of CPU = XiangShan.

[poemonsense]

Is this a bug in Spike?

[Anzooooo]

Is this a bug in Spike?

I can't be sure exactly, because the specification doesn't say anything specific about Zicclsm. And we can't be sure if Spike is doing the right thing.
Our understanding is that if the software handles cross-page misalignment, it will also split the cache into a low page and a high page. If the low page can be accessed normally, it will be accessed normally. If the high page is page fault , an exception will be generated for the high page.
However, this does not prove anything, maybe I should raise an issue in Spike.

[poemonsense]

However, this does not prove anything, maybe I should raise an issue in Spike.

It's better to ask this in Spike.

I think it look strange for an instruction to partially take effect when it causes an exception.

[Anzooooo]

However, this does not prove anything, maybe I should raise an issue in Spike.

It's better to ask this in Spike.

I think it look strange for an instruction to partially take effect when it causes an exception.

okk

[Anzooooo]

However, this does not prove anything, maybe I should raise an issue in Spike.

It's better to ask this in Spike.

I think it look strange for an instruction to partially take effect when it causes an exception.

It's legal, see:
riscv-software-src#1867 (comment)