This project simulates the overlapping Moore Design for Sequence Detection where it toggles the output high for a certain input sequence. Over here the example is taken for 1010 for detection.
Sequence detector is used to detect a particular type of sequence. It goes High or (bit 1) when it detects a particular sequence inside the input or else it stays Low or (bit 0). This design consists of 5 different states namely, S0,S1,S2,S3,S4. This design sets the output High or (bit 1) only if the sequence '1010' is received and since it's overlapping, it will continue to takes inputs after that respond accordingly.
Sequence Detector uses in real life
- Elevator in our building or mall is an example of moore design where we give input to reach a particular level (consider that to a state) and then we change the states (climb up or down) and it does not need any input at that point.
- Used when we want to perform certain work for a certain input instructions in machines.For example, when robot is designed to do some work.
Mainly two types of FSM are known, Moore and Mealy machine. In Moore, output state is only defined with the help of current input contrary to how a Mealy machine works which takes current state as well as input to determine the output.Our major focus will be on Sequence Detection using Moore Finite State Machine (FSM).
Below is the explanations of how the design works and also shown the workflow for better understanding.
- S0 (Reset or Zero State) Design of the Moore machine starts with the state S0 where we receive our first input signal. If we receive bit 1, we move to the next state of S1 or else we loop back to this state. We can also refer this state as the Reset State because every time we do not get the next desired input bit, we can always hop back to this state and restart the process.
- S1 (One State) We now have received the bit 1 and on receiving the bit 1 again, we will stay in this state, or else we move to next state of S2.
- S2 (OneZero State) We will advance to next state of S2 if we receive the bit 1 or else we will go back to state S0 because the sequence will be broken now.
- S3(OneZeroOne State) On receiving the bit 0, we will advance to next state or else we will move back to S1 state on receiving bit 1.
- S4 (OneZeroOneZero State) If we receive the bit 0, we will be going to state S0 as we can continue it for the next sequence or we will move to state S3 if we receive the bit 1. Irrespective of what bit is recieved in this state, output will trigger to high and then change corresponding to the inputs provided. Below shown is the wave file's output n testing the verilog code out against the testbench provided
Icarus Verilog is an implementation of the Verilog hardware description language. We have used this for our implementations of Sequence Detection.
GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing
Open the terminal on your mac and type this command to install iverilog and gtkwave
brew install icarus-verilog
brew install --cask gtkwave
To clone this repository and clone this netlist files for simulation, type the following commands.
Note: First command is to change your current directory to the the directory where you want to clone. If you are already in the directory, you can ignore it
cd (to a directory where you want to clone)
git clone https://github.com/ParasVekariya/Physical-Design-Of-ASIC-s.git
cd Physical-Design-Of-ASIC-s
iverilog iiitb_sdMoore.v iiitb_sdMoore_tb.v
./a.out
gtkwave test.vcd
Note : After writing ./a.out (if done manually), you will have to suspend it to get to the next step. Control + Z(^ + z) can be used for suspension.
For simulaion, I have used GTKWave tool. After suspending the output file, you will have to manually open the .vcd file. After that add the traces or signal for generating the output as shown.
Synthesis means transforming RTL design to gate level netlist with the constraints specified as per the designer. Synthesis is process as follows:
- Converting the RTL to simple logic gates.
- Mapping those gates to actual technology available gates.
- Optimizing the design while retaining the constraints.
Synthesizer is a tool that is used to synthesize the design. In my case, I have used yosys tool for synthesys.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
For yosys intallation (development purpose), please follow this GitHub repository. For yosys intallion through terminal, copy the command
brew install yosys
After installing yosys we need to write a yosys_run.sh, which is a yosys script file to synthesize the design
NOTE : Identify the .lib file in the lib folder of this cloned repo. After that replace the underlined path with your local machine's path.
Now, on the terminal inside the cloned repo folder, run the commands.
yosys
And it will open an interactive yosys terminal.
yosys> script yosys_run.sh
It will generate the synthesys for our design. It will take 6 different steps to complete the synthesis.
yosys> stat
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met. Folllowing are the commands to run the GLS simulation:
iverilog -DFUNTIONAL -DUNIT_DELAY=#1 verilog_model/primitives.v verilog_model/sky130_fd_sc_hd.v synth_iiitb_sdMoore.v iiitb_sdMoore_tb.v
./a.out
gtkwave test2.vcd
Note: If you are on a mac, you will have to manually open the .vcd file as it wont open from the terminal throught the code shown above.
The gtkwave output for the netlist should match the output waveform of the RTL design, since the inputs and outputs are same for synthesized netlist file and RTL file, we can use the same testbench for both.
Observing the above two images, we see that both the outputs post synthesis and pre synthesis are same. From here on, we will start the layout process.
brew install --cask docker
Above brew command will download the docker for mac.Once downloaded, open the spotlight ( cmd + space), type in docker and open the app. It requires some permission while opening the app which should be allowed, and then a whale icon will appear in the the menu bar which indicates that docker is ruunig. Now you can close the application but the docker will still run in the background.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII. To run this design as per screenshots go to your design folder and perform the cloning process, else go to home directory and perform the commands nothing will change except the paths in the magic commandline.
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
make
make test
Make test usually takes 5 minutes to complete.
Magic tool is used for visualization of the floorplan and placement. Below given are the steps for installation of magic on macOS.
Note: Before installing magic, tcl-tk libraries should be installed. And the libraries are to be imported from /usr/local/opt2/. For more information please visit GitHub link of magic
brew install tcl-tk
git clone https://github.com/RTimothyEdwards/magic
cd magic/
./configure --with-tcl=/usr/local/opt2/tcl-tk/lib --with-tk=/usr/local/opt2/tcl-tk/lib --x-includes=/opt/X11/include --x-libraries=/opt/X11/lib CFLAGS=-Wno-error=implicit-function-declaration
make
make install
It might take some time to complete the installtion process.
A Custom Inverter Cell is required to create an inverter that can be tweaked based on our requirements and locally used in our design files.
Run the following commands in the terminal for generating the inverter cell
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
cd vsdstdcelldesign
cp ./libs/sky130A.tech sky130A.tech
magic -T sky130A.tech sky130_inv.mag &
Two windows will be displayed, where one will show the magic display and other one is tcl console.
The above layout can be seen in the magic viewport.The design can be verified here and different layers can be seen and examined by selecting the area of examination and typing what in the tcl window.
To extract Spice netlist, type the following commands in tcl window.
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
cthresh 0 rthresh 0 are for extract parasitic capacitances and resitances from the netlist.
After this step we will have to edit the sky130_inv.spice file that will be located inside the vsdstdcelldesign folder.
Final contents of sky130_inv.spice and save the file.
For installation og ngspice
brew install ngspice
Now opne the terminal in the folder where the sky130_inv.spice is located and type the following code.
ngspice sky130_inv.spice
Now we can the plot the graph for the inverter using following commands
plot y vs time a
Four timing parameters are used to characterize the inverter standard cell:
- Rise time: Time taken for the output to rise from 20% of max value to 80% of max value
Rise time = (2.23843 - 2.17935) = 59.08ps - Fall time- Time taken for the output to fall from 80% of max value to 20% of max value
Fall time = (4.09291 - 4.05004) = 42.87ps - Cell rise delay = time(50% output rise) - time(50% input fall)
Cell rise delay = (2.20636 - 2.15) = 56.36ps - Cell fall delay = time(50% output fall) - time(50% input rise)
Cell fall delay = (4.07479 - 4.05) = 24.79ps
To get a grid and to ensure the ports are placed correctly we can use this command in the tcl console
grid 0.46um 0.34um 0.23um 0.17um
To save the file with a different name, use the folllowing command in tcl window
save sky130_vsdinv.mag
Now open the sky130_vsdinv.mag using the magic command in terminal
magic -T sky130A.tech sky130_vsdinv.mag
In the tcl window type the following command to generate sky130_vsdinv.lef
lef write
The layout for the design we have been working on can be created using OpenLANE. But before this we have to perform some preparatory steps to run our custom design in OpenLANE. Navigate to the openlane folder and run the following commands:
cd designs
mkdir iiitb_sd
cd iiitb_sd
touch config.json
mkdir src
cd src
Next copy iiitb_seq_det_moore_fsm.v, sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef in the src folder. The iiitb_sdMoore.v should be copied from the main repository, and the whole layout procedure will be carried out on this RTL design file.
Next we shall edit the cofig.json file
In this file the DESIGN_NAME corresponds to the name of the module in your design file also note to change the CLOCK_PORT and CLOCK_NET variables as per clock used in your design file.
Save all the changes made above and navigate to the OpenLane folder in terminal and run the command Note: You will have to start docker explicitly to be able to mount when compiling in macOS.
sudo make mount
After entering the openlane container give the following command for a step by step procedure:
./flow.tcl -interactive
This will open the tcl console. Type the comamnds every time we access the tcl console
package require openlane 0.9
prep -design iiitb_sd
The following commands are to merge the external lef files to the merged.nom.lef. In our case sky130_vsdiat.lef is the external .lef file that gets merged to the lef file.
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
After the merging step the contents of the merged.nom.lef file should contain the Macro definition of sky130_vsdinv
run_synthesis
Setup and Hold Slack
The sky130_vsdinv should also reflect in your netlist after Synthesis
run_floorplan
Floorplan report
Die Area
Core Area
Navigate to results -> floorplan and type the Magic command in terminal to open the floorplan
magic -T /Users/paras/Desktop/code/iiitb_sd/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_sdMoore.def &
Bottom view before placement ,here its currently stacked.
run_placement
Navigate to results->placement and type the Magic command in terminal to open the placement view
magic -T /Users/paras/Desktop/code/iiitb_sd/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_sdMoore.def &
Zooming the layout we can find the sky130 inverter inside th design.
The sky130_vsdinv should also reflect in your netlist after placement
run_cts
run_routing
Navigate to results->routing and type the Magic command in terminal to open the placement view.
magic -T /Users/paras/Desktop/code/iiitb_sd/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_sdMoore.def &
Routing View
Wiring in routing.
Inverter in routing.
Area Report by magic:
The sky130_vsdinv should also reflect in your netlist after routing
Area = 7842.509 um^2
Below given sta command is for macOs. For other OS it might look different
./sta
% read_liberty -max /Users/paras/Desktop/code/asic/OpenLane/designs/iiitb_sd/src/sky130_fd_sc_hd__fast.lib
% read_liberty -min /Users/paras/Desktop/code/asic/OpenLane/designs/iiitb_sd/src/sky130_fd_sc_hd__slow.lib
% read_verilog /Users/paras/Desktop/code/asic/OpenLane/designs/iiitb_sd/runs/RUN_2022.09.28_05.54.35/results/routing/iiitb_sdMoore.resized.v
% link_design iiitb_sdMoore
% read_sdc /Users/paras/Desktop/code/asic/OpenLane/designs/iiitb_sd/runs/RUN_2022.09.28_05.54.35/results/cts/iiitb_sdMoore.sdc
% read_spef /Users/paras/Desktop/code/asic/OpenLane/designs/iiitb_sd/runs/RUN_2022.09.28_05.54.35/results/routing/iiitb_sdMoore.nom.spef
% set_propagated_clock [all_clocks]
% report_checks
% report_clock_properties
Performance = 1/(clockPeriod - slack) = 1/(6-3.92)ns = 480 MHz
Flop Ratio ={Ratio of total number of flip flops / Total number of cells present in the design} = 6/22 = 0.27
Internal Power = 132 uW (84.7%)
Switching Power = 23.8 uW (15.3%)
Leakage Power = 0.301 nW (0.00%)
Total Power = 155 uW (100%)
- Paras Vekariya
- Kunal Ghosh
Kunal Ghosh, Director, VCD Corp. Pvt. Ltd.