Skip to content

Conversation

Copy link
Contributor

Copilot AI commented Nov 27, 2025

Implements M68000 ROL (Rotate Left) and ROR (Rotate Right) instructions per the specification.

Supported modes

  • Register with immediate count: ROL.b #3, D0 — count 1-8 (0 encodes 8)
  • Register with register count: ROL.w D1, D0 — count mod 64
  • Memory: ROL.w (A0) — word only, 1-bit rotation

Condition codes

  • X: unchanged
  • N: set if MSB of result set
  • Z: set if result zero
  • V: always cleared
  • C: last bit rotated out (cleared when count=0)

Files added

  • include/GenieSys/CpuOperations/ROL.h / ROR.h
  • src/CpuOperations/ROL.cpp / ROR.cpp
  • test/CpuOperations/ROLTest.cpp / RORTest.cpp

Example

// ROL.b #1, D0 with D0=0x80
// Result: D0=0x01, C=1 (bit 7 rotated out to bit 0)

// ROR.b #1, D0 with D0=0x01  
// Result: D0=0x80, C=1 (bit 0 rotated out to bit 7)

36 new tests, all 805 tests passing.

Original prompt

This section details on the original issue you should resolve

<issue_title>Implement ROd</issue_title>
<issue_description>Operation: Destination Rotated By < count > → Destination

Assembler ROd Dx,Dy

Syntax: ROd # < data > ,Dy ROd < ea > where d is direction, L or R

Attributes: Size = (Byte, Word, Long)

Description:
Rotates the bits of the operand in the direction specified (L or R). The extend
bit is not included in the rotation. The rotate count for the rotation of a register is
specified in either of two ways:

  1. Immediate—The rotate count (1 – 8) is specified in the instruction.
  2. Register—The rotate count is the value in the data register specified in the instruction, modulo 64.
    The size of the operation for register destinations is specified as byte, word, or long.
    The contents of memory, (ROd < ea > ), can be rotated one bit only, and operand size
    is restricted to a word.
    The ROL instruction rotates the bits of the operand to the left; the rotate count determines the number of bit positions rotated. Bits rotated out of the high-order bit go to the
    carry bit and also back into the low-order bit.
    .
    The ROR instruction rotates the bits of the operand to the right; the rotate count determines the number of bit positions rotated. Bits rotated out of the low-order bit go to the
    carry bit and also back into the high-order bit.

Condition Codes:
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Set according to the last bit rotated out of the operand; cleared when the rotate
count is zero. </issue_description>

<agent_instructions>Please implement this ticket following existing coding practices found in the GenieSys repository.</agent_instructions>

Comments on the Issue (you are @copilot in this section)


💡 You can make Copilot smarter by setting up custom instructions, customizing its development environment and configuring Model Context Protocol (MCP) servers. Learn more Copilot coding agent tips in the docs.

Copilot AI and others added 2 commits November 27, 2025 23:58
Co-authored-by: PaulTrampert <5550942+PaulTrampert@users.noreply.github.com>
…ments

Co-authored-by: PaulTrampert <5550942+PaulTrampert@users.noreply.github.com>
Copilot AI changed the title [WIP] Implement ROd instruction for bit rotation Implement ROL and ROR (rotate left/right) instructions Nov 28, 2025
Copilot AI requested a review from PaulTrampert November 28, 2025 00:07

namespace GenieSys {
class ROL : public CpuOperation {
private:
Copy link
Owner

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

We should have a constant here to represent the base opcode. Define the constant using binary representation rather than hex or base-10.

The value should be 0b1110001000011000 for ROL and 0b111000000011000 for ROR.

#include "../BitMask.h"

namespace GenieSys {
class ROL : public CpuOperation {
Copy link
Owner

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

:thought: Maybe merge this with ROR and extract the direction as a bitmask on bit 8.

return countRegMask.getWidth() + sizeMask.getWidth() + irMask.getWidth() + regMask.getWidth();
}

std::vector<uint16_t> GenieSys::ROL::getOpcodes() {
Copy link
Owner

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

getOpcodes should be a single call to getPossibleOpcodes. The first parameter should be the base opcode, and the second should be a vector of the addresses of all the operand bitmasks.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

Implement ROd

2 participants