List of useful materials on FPGA topic -- FPGA useful list

Content

• Websites
• YouTube
• Telegram
• Books
• GitHub
  • CPU
  • Tools
  • Peoples
  • Others

Websites

• HDLBits
• TestBench.in
• Asic World
• FPGA Tutorial
• Chipverify
• VLSI Verify
• Circuit Cove
• Verificatioin Guide
• NANDLAND
• OpenCores
• FPGA-Systems
• Marsohod
• Истовый Инженер
• EDA playground

YouTube

• Chip Design School
• Разработка аппаратного обеспечения
• Архитектура и язык ассемблера RISC-V
• Introduction to FPGA
• Архитектура ЭВМ
• Основы программирования встраиваемых систем
• Lectures Verilog
• Lectures STM32 v2
• SPI Project in FPGA - Ambient Light Sensor
• UART
• LFSR
• AXI and AXI Stream
• Zynq
• Уроки FPGA
• Цифровая обработка сигналов
• Основы программирования
• Harvard CS50 на русском
• Архитектуры процессорных систем
• Архитектура компьютеров и Операционные системы

Telegram

• Записки CPU designer'a
• Xilinx Zynq 7000
• VFA (Verification For All)
• FPGA-Systems
• DocsTech
• Истовый Инженер
• VLSI HUB
• IP Cores
• FPGAASIC

Books

• ПРОГРАММИРОВАНИЕ FPGA ДЛЯ НАЧИНАЮЩИХ
• ЦИФРОВАЯ СХЕМОТЕХНИКА И АРХИТЕКТУРА КОМПЬЮТЕРА: RISC-V
• ЦИФРОВАЯ СХЕМОТЕХНИКА И АРХИТЕКТУРА КОМПЬЮТЕРА. ДОПОЛНЕНИЕ ПО АРХИТЕКТУРЕ ARM
• ЦИФРОВОЙ СИНТЕЗ: RISC-V
• ЛОГИЧЕСКОЕ ПРОЕКТИРОВАНИЕ И ВЕРИФИКАЦИЯ СИСТЕМ НА SYSTEM VERILOG
• ПРОГРАММИРОВАНИЕ НА ЯЗЫКЕ АССЕМБЛЕРА RISC-V
• АРХИТЕКТУРА ВСТРАИВАЕМЫХ СИСТЕМ
• РЕВЕРС-ИНЖИНИРИНГ ВСТРАИВАЕМЫХ СИСТЕМ
• Джон Л. Хеннесси, Дэвид А. Паттерсон "Компьютерная архитектура. Количественный подход"

GitHub

Topics

• CPU
• Tools
• Peoples
• Others

CPU

• schoolMIPS - A small MIPS CPU core originally based on Sarah L. Harris MIPS CPU ("Digital Design and Computer Arhitecture" by David Money Harris and Sarah L Harris).
• RARS - RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs.
• schoolRISCV - Tiny RISCV CPU. Originally based on Sarah L. Harris MIPS CPU ("Digital Design and Computer Arhitecture" by David Money Harris and Sarah L Harris) and schoolMIPS project.
• LUMOS - Multicycle RISC-V processor that implements a subset of RV32I instruction set, designed for educational use in computer organization classes at Iran University of Science and Technology.
• PicoRV32 - PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set.
• MIRISCV - CPU core that implements ISA RV32IM.
• Ibex - Production-quality open source 32-bit RISC-V CPU that supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
• Zip CPU - The Zip CPU is a small, light-weight, RISC CPU.
• CORE-V Wally - Configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
• RISCV-DV - RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V processor verification.
• AAPG - Automated Assembly Program Generator for the RISC-V ISA.
• APS - Лекции и лабораторные по курсу «Архитектуры процессорных систем»
• NERV - NERV is a very simple single-stage RV32I processor.
• Snippy - This is an LLVM project fork containing the LLVM-snippy generator.
• VeeR-ISS - Whisper is a RISC-V instruction set simulator (ISS) developed for the verification of the Veer micro-controller.
• Spike - Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts.
• uRV - The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs.
• Hummingbirdv2 E203 Core and SoC - The Ultra-Low Power RISC-V Core
• CV32E40P - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
• CVA6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
• Vortex GPGPU - Vortex is a full-stack open-source RISC-V GPGPU
• RISC-V Debug - RISC-V Debug Support for PULP RISC-V Cores
• biRISC-V - 32-bit Superscalar RISC-V CPU
• Rocket Chip Generator - The Rocket chip generator necessary to instantiate the RISC-V Rocket Core

Tools

• SV2V - Converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs
• hdlgadgets - A human-in-the-loop training tool for rtl-developers, microarchitects and verification engineers allowing experiments with flow control and verification techniques
• DESim - Application that provides a graphical user interface (GUI) that represents some of the features of a DE1-SoC board
• openFPGALoader - Universal utility for programming FPGAs
• Digital - Easy-to-use digital logic designer and circuit simulator designed for educational purposes
• WaveDrom - Online digital timing diagram (waveform) rendering engine that uses javascript, HTML5 and SVG to convert a WaveJSON input text description into SVG vector graphics
• Yosys - Framework for RTL synthesis tools
• Verilator - SystemVerilog simulator and lint system
• Icarus Verilog - Intended to compile ALL of the Verilog HDL, as described in the IEEE-1364 standard
• GTKWave - Fully featured GTK+ based wave viewer for Unix and Win32 which reads FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing
• HDLMake - Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)
• Cocotb - Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
• PyUVM - UVM written in Python
• SVUnit - Framework for ASIC and FPGA developers writing Verilog/SystemVerilog code
• VUnit - Unit testing framework for VHDL/SystemVerilog
• GHDL - VHDL 2008/93/87 simulator
• Verilog to Routing - Open Source CAD Flow for FPGA Research
• LiteX - Framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems
• EDA Playground - The FREE IDE for SystemVerilog, Verilog, and VHDL
• MyHDL - Free open-source package for using Python as a hardware description and verification language
• Nextpnr - portable FPGA place and route tool.
• OpenLane - automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization
• SiliconCompiler - modular hardware build system ("make for silicon")
• Verible - Suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
• Svlint - SystemVerilog linter compliant with IEEE1800-2017
• SV-parser - SystemVerilog parser library fully compliant with IEEE 1800-2017
• SVls - SystemVerilog language server
• HDL support for VS Code - HDL support for VS Code with Syntax Highlighting, Snippets, Linting, Formatting
• TerosHDL - VSCode extension

Peoples

• Artin Isagholian
• Alex Forencich
• Tomasz Hemperek
• Jeff Johnson
• Russell Merrick
• Dan Gisselquist
• Stacey(FPGAs for Beginners)
• Yuri Panchul
• Stanislav Zhelnio
• Sergey Chusov
• Alexander Romanov
• Viktor Prutyanov

Others

• FPGA-Systems - FPGA-Systems repos
• Marsohod - Marsohod repos
• Chip Design School - Chip Design School repos
• Style Guides - lowRISC style guides
• Opencores Scraper - Few python scripts to clone all IP cores from opencores.org
• FreeCores - A home for open source hardware cores