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Improve: naked asm functions
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Signed-off-by: Manami Mori <manami.mori@aist.go.jp>
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Manami Mori committed Jun 15, 2024
1 parent 59968e0 commit 806ab23
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Showing 3 changed files with 94 additions and 94 deletions.
28 changes: 14 additions & 14 deletions src/hypervisor_bootloader/src/main.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -197,7 +197,7 @@ extern "C" fn efi_main(image_handle: EfiHandle, system_table: *mut EfiSystemTabl
set_up_el1();

/* Jump to EL1(el1_main) */
el2_to_el1(stack_address, el1_main as *const fn() as usize);
el2_to_el1(el1_main as *const fn() as usize, stack_address);

/* Never come here */
local_irq_fiq_restore(unsafe { INTERRUPT_FLAG.assume_init_ref().clone() });
Expand Down Expand Up @@ -1122,21 +1122,21 @@ extern "C" fn el1_main() -> ! {
exit_bootloader();
}

#[naked]
extern "C" fn el2_to_el1(stack_pointer: usize, el1_entry_point: usize) {
fn el2_to_el1(el1_entry_point: usize, el1_stack_pointer: usize) {
unsafe {
asm!(
"
msr elr_el2, x1 // x1 contains the entry point of EL1
mov x8, sp
msr sp_el1, x8
mov sp, x0 // x0 contains stack_pointer
mov x0, (1 << 7) |(1 << 6) | (1 << 2) | (1) // EL1h(EL1 + Use SP_EL1)
msr spsr_el2, x0
asm!("
msr elr_el2, {entry_point}
mov {tmp}, sp
msr sp_el1, {tmp}
mov sp, {stack_pointer}
mov {tmp}, (1 << 7) |(1 << 6) | (1 << 2) | (1) // EL1h(EL1 + Use SP_EL1)
msr spsr_el2, {tmp}
isb
eret
",
options(noreturn)
eret",
tmp = in(reg) 0u64,
entry_point = in(reg) el1_entry_point,
stack_pointer = in(reg) el1_stack_pointer,
options(noreturn)
)
}
}
20 changes: 13 additions & 7 deletions src/hypervisor_kernel/src/main.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -363,10 +363,11 @@ fn interrupt_handler_panic(s_r: &StoredRegisters, f: core::fmt::Arguments) -> !
panic!("{}", f)
}

global_asm!(
"
.section .text
.balign 0x800
global_asm!("
.section .text
.type vector_table_el2, %function
.size vector_table_el2, 0x800
.balign 0x800
vector_table_el2:
.balign 0x080
Expand Down Expand Up @@ -446,10 +447,8 @@ fiq_lower_aa32:
.balign 0x080
s_error_lower_aa32:
nop
"
);
global_asm!("
.type synchronous_lower_aa64_save_registers, %function
synchronous_lower_aa64_save_registers:
sub sp, sp, {SR_SIZE}
stp x30, xzr, [sp, #( 15 * 16)]
Expand Down Expand Up @@ -480,6 +479,9 @@ synchronous_lower_aa64_save_registers:
str x0, [sp, #( 15 * 16 + 8)]
b synchronous_lower_aa64_1
.size synchronous_lower_aa64_save_registers, . - synchronous_lower_aa64_save_registers
.type s_error_lower_aa64_save_registers, %function
s_error_lower_aa64_save_registers:
sub sp, sp, {SR_SIZE}
stp x30, xzr, [sp, #( 15 * 16)]
Expand Down Expand Up @@ -510,7 +512,9 @@ s_error_lower_aa64_save_registers:
str x0, [sp, #( 15 * 16 + 8)]
b s_error_lower_aa64_1
.size s_error_lower_aa64_save_registers, . - s_error_lower_aa64_save_registers
.type lower_aa64_restore_registers_and_eret, %function
lower_aa64_restore_registers_and_eret:
mrs x0, spsr_el2
ubfx x0, x0, #0, #4 // and x0, x0, #0b1111
Expand Down Expand Up @@ -540,5 +544,7 @@ lower_aa64_restore_registers_and_eret:
ldp x2, x3, [sp, #( 1 * 16)]
ldp x0, x1, [sp, #( 0 * 16)]
add sp, sp, {SR_SIZE}
isb
eret
.size lower_aa64_restore_registers_and_eret, . - lower_aa64_restore_registers_and_eret
", SR_SIZE = const core::mem::size_of::<StoredRegisters>());
140 changes: 67 additions & 73 deletions src/hypervisor_kernel/src/multi_core.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -227,69 +227,66 @@ fn spin_table_store_access_handler(
#[naked]
extern "C" fn cpu_boot() {
unsafe {
core::arch::asm!(
" // MIDR_EL1 & MPIDR_EL1
mrs x15, midr_el1
msr vpidr_el2, x15
mrs x16, mpidr_el1
msr vmpidr_el2, x16
core::arch::asm!("
// MIDR_EL1 & MPIDR_EL1
mrs x15, midr_el1
msr vpidr_el2, x15
mrs x16, mpidr_el1
msr vmpidr_el2, x16
// SVE
mrs x17, id_aa64pfr0_el1
ubfx x18, x17, 32, 4
cbz x18, 1f
mov x15, {MAX_ZCR_EL2_LEN}
msr S3_4_C1_C2_0, x15 // ZCR_EL2
// SVE
mrs x17, id_aa64pfr0_el1
ubfx x18, x17, 32, 4
cbz x18, 1f
mov x15, {MAX_ZCR_EL2_LEN}
msr S3_4_C1_C2_0, x15 // ZCR_EL2
1:
// GICv3~
/*ubfx x18, x17, 24, 4
cbz x18, 2f
mrs x15, icc_sre_el2
orr x15, x15, 1 << 0
orr x15, x15, 1 << 3
msr icc_sre_el2, x15
isb
mrs x15, icc_sre_el2
tbz x15, 0, 2f
msr ich_hcr_el2, xzr*/
// GICv3~
mrs x15, icc_sre_el2
and x16, x15, 1
cbz x16, 2f
mov x17, 0xf
msr icc_sre_el2, x16
msr ich_hcr_el2, xzr
isb
2:
// A64FX
mov x15, {A64FX}
cbz x15, 3f
msr S3_4_C11_C2_0, xzr // IMP_FJ_TAG_ADDRESS_CTRL_EL2
3:
// A64FX
mov x15, {A64FX}
cbz x15, 3f
msr S3_4_C11_C2_0, xzr // IMP_FJ_TAG_ADDRESS_CTRL_EL2
ldp x1, x2, [x0, 16 * 0]
ldp x3, x4, [x0, 16 * 1]
ldp x5, x6, [x0, 16 * 2]
ldp x7, x8, [x0, 16 * 3]
ldp x9, x10, [x0, 16 * 4]
ldp x11, x12, [x0, 16 * 5]
3:
ldp x1, x2, [x0, 16 * 0]
ldp x3, x4, [x0, 16 * 1]
ldp x5, x6, [x0, 16 * 2]
ldp x7, x8, [x0, 16 * 3]
ldp x9, x10, [x0, 16 * 4]
ldp x11, x12, [x0, 16 * 5]
mov sp, x0
add sp, sp, #(16 * 6)
msr cnthctl_el2, x1
msr cntvoff_el2, xzr
msr cptr_el2, x2
msr ttbr0_el2, x3
msr mair_el2, x4
msr tcr_el2, x5
msr vbar_el2, x6
msr vttbr_el2, x7
msr vtcr_el2, x8
msr sctlr_el2, x9
msr hcr_el2, x10
mov sp, x0
add sp, sp, #(16 * 6)
msr cnthctl_el2, x1
msr cntvoff_el2, xzr
msr cptr_el2, x2
msr ttbr0_el2, x3
msr mair_el2, x4
msr tcr_el2, x5
msr vbar_el2, x6
msr vttbr_el2, x7
msr vtcr_el2, x8
msr sctlr_el2, x9
msr hcr_el2, x10
mov x1, (1 << 7) |(1 << 6) | (1 << 2) | (1) // EL1h(EL1 + Use SP_EL1)
msr spsr_el2, x1
msr elr_el2, x11
mov x0, x12
eret
", MAX_ZCR_EL2_LEN = const cpu::MAX_ZCR_EL2_LEN,
A64FX = const cfg!(feature = "a64fx") as u64,
options(noreturn))
mov x1, (1 << 7) |(1 << 6) | (1 << 2) | (1) // EL1h(EL1 + Use SP_EL1)
msr spsr_el2, x1
msr elr_el2, x11
mov x0, x12
isb
eret",
MAX_ZCR_EL2_LEN = const cpu::MAX_ZCR_EL2_LEN,
A64FX = const cfg!(feature = "a64fx") as u64,
options(noreturn))
}
}

Expand All @@ -301,24 +298,21 @@ extern "C" fn cpu_boot() {
#[naked]
extern "C" fn spin_table_boot() {
unsafe {
core::arch::asm!(
"
.align 3
adr x1, 2f
core::arch::asm!("
.align 3
adr x1, 2f
1:
//ldaxr x0, [x1]
ldr x0, [x1]
cbz x0, 1b
//stlxr w2, xzr, [x1]
str xzr, [x1]
//cbnz w2, 1b
nop
b {CPU_BOOT}
//ldaxr x0, [x1]
ldr x0, [x1]
cbz x0, 1b
//stlxr w2, xzr, [x1]
str xzr, [x1]
//cbnz w2, 1b
nop
b {CPU_BOOT}
2:
.quad 0
",
CPU_BOOT = sym cpu_boot,
options(noreturn)
)
.quad 0",
CPU_BOOT = sym cpu_boot,
options(noreturn))
}
}

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