Tritium Project

This is a research project

This project is not fully intended to get a perfectly functional computer out to the market, but rather, it is intended to get the concept of ternary computing out to the public so more people will start researching ternary computing as an alternative to binary computing.

What does balanced ternary mean?

Normal computers process data in binary which means two states, a one and a zero. Ternary is similar except operating on three states. In balanced ternary, there is a negative (i), neutral (0), and positive (1) which means numbers are naturally signed thus simplifying the architecture and general logic. Ternary also has the best radix efficiency for any integer base of 1.0046 where binary is 1.0615 with base e, 1.0000 being the most efficient. A 'trit' is the ternary analogue of a bit which stores an i (-1), 0, or 1.

Has this been done before?

There are many projects similar to this but they either haven’t gone very far, closed source and secretive, or dead. The main inspiration for this project is the Russian Setun computer, more specifically the Setun-70 which has an 18 trit word and 81 words of memory with a magnetic drum holding more memory.

Directory Structure

• docs - contains documentation on the project and lab results

• kicad - contains the kicad project files for each part

  • components - contains all complex multigate circuits

  • gates - contains all ternary gates and their panelized PCBs

  • logic - contains logical schematics of circuits using logic gates instead of transistors

• library - contains all of the kicad libraries such as the footprints, spice models, and symbols

Possible final computer variants

Tritium-6

A 6-trit computer that is cheap and simple to make where the instructions more closely resemble microcode rather than instructions.

Design Goals

• Around or less than $250 in components

• Have the ability to communicate with binary components

• Use easily sourcable parts

• One clock cycle per instruction

Tritium-27

A full scale computer that mirrors RISC-V in capability and instruction set.

Design Goals

• Around or less than $1000 in components

• Have the ability to communicate with binary components

• Use easily sourcable parts

Current Status

The gates from OSHPark came but I’ve hit a bit of a time and financial crunch so I don’t quite have the time to work on the physical part of the project. I’m currently working with a local college professor to write up a better ISA than the previous versions for a machine that I could follow that wouldn’t be too expensive to implement. I’ve decided that the decoding logic for the control module may be too expensive to implement so I will see if I can use a binary EEPROM using encoded balanced ternary as a lookup table and then convert the inputs back to native balanced ternary.