compile and test also while running test.

Readon · Nov 3, 2023 · a3f265e · a3f265e
1 parent bef7ed0
commit a3f265e
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/test_template.sh b/test_template.sh
@@ -23,10 +23,12 @@ do_test(){
     sed -i "s/\(val spinalVersion = \)\(\".*\"\)/\1\"${_spinal_version}\"/" build.sbt
     sed -i "s/\(scalaVersion := \)\(\".*\"\)/\1\"${_scala_full_version}\"/" build.sbt
 
+    ${SBT_CMD} -Dsbt.offline=true "compile" || exit
     ${SBT_CMD} -Dsbt.offline=true "runMain projectname.MyTopLevelVerilog" || exit
     ${SBT_CMD} -Dsbt.offline=true "runMain projectname.MyTopLevelVhdl" || exit
     ${SBT_CMD} -Dsbt.offline=true "runMain projectname.MyTopLevelSim" || exit
     ${SBT_CMD} -Dsbt.offline=true "runMain projectname.MyTopLevelFormal" || exit
+    ${SBT_CMD} -Dsbt.offline=true "test" || exit
 
     cd ..
 }