v0.23.0

Changes

• Remove unused lmx6.0 dependency

v0.22.0-rc1

Changes

• Adds workaround for kernel names longer than Vivado 2018.2 supports

v0.21.0: Upgrade library to be compatible with Xilinx SDAccel 2018.2

Changes

• Upgrade library to be compatible with Xilinx SDAccel 2018.2

SMI Library workaround for legacy compiler loop evaluation bug

This is a workaround for the legacy compiler bug, whereby a channel pop in the conditional term of a loop only occurs on entry to the loop and not on each subsequent iteration.

SMI Library Fixes For Rio Compiler

Introduces correctness fixes for the SMI library that are required by the new LLVM based Rio compiler.

v0.19.0

Deleted duplicate Verilog components from public SDAccel repository.

v0.18.0

Changes

• Make SDK non-blocking so data can be loaded and retrieved while the FPGA is running
• Zero-initialise World so it can be inspected (e.g. you can now read the input data out)

Enhanced Verilog AXI configuration options.

Added Verilog configuration options for masking the AXI cache options and enabling AXI-3 style support for the write ID signal.

v0.17.0: Merge pull request #2 from ReconfigureIO/feature/add-smi

Add SMI sub package

v0.15.1

Add clean.