Riolu / Pipelined-CPU Public

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A design of 5-stage pipelined CPU, course project of EI332.

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
db		db
greybox_tmp		greybox_tmp
incremental_db		incremental_db
output_files		output_files
.gitattributes		.gitattributes
Pipeline.qpf		Pipeline.qpf
README.md		README.md
add_datamem.mif		add_datamem.mif
add_instmem.mif		add_instmem.mif
alu.v		alu.v
alu.v.bak		alu.v.bak
cla32.v		cla32.v
dff32.v		dff32.v
dffe32.v		dffe32.v
exp3_instmem.mif		exp3_instmem.mif
exp_instmem.mif		exp_instmem.mif
io_input_reg.v		io_input_reg.v
io_output_reg.v		io_output_reg.v
io_output_reg.v.bak		io_output_reg.v.bak
led.v		led.v
lpm_ram_dq_dram.qip		lpm_ram_dq_dram.qip
lpm_ram_dq_dram.v		lpm_ram_dq_dram.v
lpm_rom_irom.qip		lpm_rom_irom.qip
lpm_rom_irom.v		lpm_rom_irom.v
lpm_rom_irom_bb.v		lpm_rom_irom_bb.v
mux2x32.v		mux2x32.v
mux2x5.v		mux2x5.v
mux4x32.v		mux4x32.v
pip_top.pin		pip_top.pin
pip_top.qsf		pip_top.qsf
pip_top.qsf.bak		pip_top.qsf.bak
pip_top.qws		pip_top.qws
pip_top.v		pip_top.v
pip_top.v.bak		pip_top.v.bak
pipedereg.v		pipedereg.v
pipedereg.v.bak		pipedereg.v.bak
pipeemreg.v		pipeemreg.v
pipeemreg.v.bak		pipeemreg.v.bak
pipeexe.v		pipeexe.v
pipeexe.v.bak		pipeexe.v.bak
pipeid.v		pipeid.v
pipeid.v.bak		pipeid.v.bak
pipeif.v		pipeif.v
pipeif.v.bak		pipeif.v.bak
pipeir.v		pipeir.v
pipeir.v.bak		pipeir.v.bak
pipemem.v		pipemem.v
pipemem.v.bak		pipemem.v.bak
pipemwreg.v		pipemwreg.v
pipemwreg.v.bak		pipemwreg.v.bak
pipepc.v		pipepc.v
pipepc.v.bak		pipepc.v.bak
regfile.v		regfile.v
regfile.v.bak		regfile.v.bak
sc_computer.qsf		sc_computer.qsf
sc_cpu.v		sc_cpu.v
sc_cu.v		sc_cu.v
sc_cu.v.bak		sc_cu.v.bak
sc_datamem.mif		sc_datamem.mif
sc_datamem.v		sc_datamem.v
sc_instmem.mif		sc_instmem.mif
sc_instmen.v		sc_instmen.v