Here is a RISC-V Vector Instruction Set SoC implemented using Chisel3.
You should now have a working Chisel3 project.
You can run the included test with:
sbt testYou should see a whole bunch of output that ends with something like the following lines
[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
[info] All tests passed.
[success] Total time: 5 s, completed May 16, 2023 12:18:44 PM
If you see the above then...
The project is organized as follows:
And the SoC structure:
RVVSoC is under the BSD-2-Clause license. See the LICENSE file for details.