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ALU, DFF, Parity, Parallel2Serial
ALU, DFF, Parity, Parallel2Serial
 
 
ASMD, BCD, Comparator, Universal Shift Register
ASMD, BCD, Comparator, Universal Shift Register
 
 
Counter and IIR
Counter and IIR
 
 
Digital Watch
Digital Watch
 
 
Ex-3_2_Bin, Manchester, Traffic State Machine
Ex-3_2_Bin, Manchester, Traffic State Machine
 
 
General RAM
General RAM
 
 
Mealy and Moore
Mealy and Moore
 
 
UART
UART
 
 
Watch on LCD
Watch on LCD
 
 
2 Bit Comparator Testbench.v
2 Bit Comparator Testbench.v
 
 
2 Bit Comparator.v
2 Bit Comparator.v
 
 
256B RAM Testbench.v
256B RAM Testbench.v
 
 
265B RAM.v
265B RAM.v
 
 
4 Bit Comparator Behavioural Testbench.v
4 Bit Comparator Behavioural Testbench.v
 
 
4 Bit Comparator Behavioural.v
4 Bit Comparator Behavioural.v
 
 
4 Bit Comparator Dataflow Testbench.v
4 Bit Comparator Dataflow Testbench.v
 
 
4 Bit Comparator Dataflow.v
4 Bit Comparator Dataflow.v
 
 
4 Bit Comparator Testbench.v
4 Bit Comparator Testbench.v
 
 
4 Bit Comparator.v
4 Bit Comparator.v
 
 
4 Bit Multiplier Testbench.v
4 Bit Multiplier Testbench.v
 
 
4 Bit Multiplier.v
4 Bit Multiplier.v
 
 
BCD to 7 Segment Dataflow Testbench.v
BCD to 7 Segment Dataflow Testbench.v
 
 
BCD to 7 Segment Dataflow.v
BCD to 7 Segment Dataflow.v
 
 
BCD to 7 Segment Testbench.v
BCD to 7 Segment Testbench.v
 
 
BCD to 7 Segment.v
BCD to 7 Segment.v
 
 
Clock Divider Testbench.v
Clock Divider Testbench.v
 
 
Clock Divider.v
Clock Divider.v
 
 
Comparator Dataflow Testbench.v
Comparator Dataflow Testbench.v
 
 
Comparator Dataflow.v
Comparator Dataflow.v
 
 
Counter 1Hz Testbench.v
Counter 1Hz Testbench.v
 
 
Counter 1Hz.v
Counter 1Hz.v
 
 
Counter Testbench.v
Counter Testbench.v
 
 
Counter.v
Counter.v
 
 
DFF Testbench.v
DFF Testbench.v
 
 
DFF.v
DFF.v
 
 
Decoder 2-4 Dataflow.v
Decoder 2-4 Dataflow.v
 
 
Decoder 2-4 Testbench.v
Decoder 2-4 Testbench.v
 
 
Decoder 2-4.v
Decoder 2-4.v
 
 
Decoder 24 Dataflow Testbench.v
Decoder 24 Dataflow Testbench.v
 
 
Decoder 3-8 Dataflow Testbench.v
Decoder 3-8 Dataflow Testbench.v
 
 
Decoder 3-8 Dataflow.v
Decoder 3-8 Dataflow.v
 
 
Decoder 3-8 Testbench.v
Decoder 3-8 Testbench.v
 
 
Decoder 3-8.v
Decoder 3-8.v
 
 
Full Adder 1 Bit Testbench.vhd
Full Adder 1 Bit Testbench.vhd
 
 
Full Adder 1 Bit.v
Full Adder 1 Bit.v
 
 
Full Adder 3 Bit Testbench.v
Full Adder 3 Bit Testbench.v
 
 
Full Adder 3 Bit.v
Full Adder 3 Bit.v
 
 
Full Adder Dataflow Testbench.v
Full Adder Dataflow Testbench.v
 
 
Full Adder Dataflow.v
Full Adder Dataflow.v
 
 
Half Adder Testbench.v
Half Adder Testbench.v
 
 
Half Adder.v
Half Adder.v
 
 
Mux 8-1 Testbench.v
Mux 8-1 Testbench.v
 
 
Mux 8-1.v
Mux 8-1.v
 
 
Q2 24-2-20 Testbench.v
Q2 24-2-20 Testbench.v
 
 
Q2 24-2-20.v
Q2 24-2-20.v
 
 
README.md
README.md
 
 
TFF Testbench.v
TFF Testbench.v
 
 
TFF.v
TFF.v
 
 

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Verilog RTL

Some generic Verilog and VHDL profects upon which complex hardware architectures are to be made. Writing efficient RTL is what enhances Instructions/second and what makes the chip designs faster.

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