Compressed Instruction Decoder for RV32I using TL-Verilog and M5

This repository aims to design the decoder/decompressor for Compressed Instructions using Transaction-Level Verilog and M5 Macro-preprocessor Library developed by Redwood EDA.

Currently supports 32-bit and Integer based instructions only. Also has support for all instruction formats like ones below :

All the instructions are taken from the RISC-V Technical specification which can be found here.