Test merge from upstream

[akashlevy]

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Important

Add sort command to synthesis scripts and remove redundant sort calls from optimization passes, with updates to signal comparison logic in opt_clean.cc.

• Behavior:
  • Add sort command to prep.ys, prep.cc, synth_gowin.cc, and synth_xilinx.cc to ensure sorting is done at specific stages.
  • Remove redundant sort calls from opt.cc and opt_clean.cc to streamline optimization passes.
• Functions:
  • In opt_clean.cc, modify compare_signals() to ensure correct signal comparison by adding a condition to compare offsets when wires are the same.
  • In opt_clean.cc, change rmunused_module_signals() to use the updated compare_signals() logic.
• Misc:
  • Minor code reordering and cleanup in opt_clean.cc to improve readability and maintainability.

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[greptile-apps]

Greptile Overview

Greptile Summary

This PR is a merge from upstream that shifts sorting to be explicit in scripts/passes and tweaks a few internals.

Key changes:

• Removes implicit Design::sort() calls from the opt and opt_clean/clean passes, and instead adds explicit sort steps in scripts (prep, synth_gowin, synth_xilinx) and the documentation macro example.
• Adds an early return in RTLIL::Module::remove(const pool<Wire*>&) when the pool is empty.
• Adjusts representative-selection logic in passes/opt/opt_clean.cc (compare_signals + call-site inversion) to refine canonicalization within connected signal groups.

No must-fix issues were found in the diff: the new compare_signals tie-breaker for bits on the same wire is consistent with the “pick s2 over s1” contract, and the sort relocation keeps determinism while avoiding doing it implicitly in opt/opt_clean.

Confidence Score: 5/5

• This PR is safe to merge with minimal risk.
• Changes are small, localized, and primarily move sorting from implicit pass behavior to explicit script steps; the only functional logic tweak (signal representative selection) remains a deterministic comparison and aligns with existing intent.
• passes/opt/opt_clean.cc

Important Files Changed

Filename	Overview
docs/source/code_examples/macro_commands/prep.ys	Adds an explicit sort command to the prep macro example after opt -fast for deterministic ordering.
kernel/rtlil.cc	Adds an early return in RTLIL::Module::remove(pool<Wire*>) when the input pool is empty to avoid unnecessary work.
passes/opt/opt.cc	Removes design->sort() from the end of the opt pass, relying on callers/scripts to sort explicitly if needed.
passes/opt/opt_clean.cc	Adjusts representative-selection logic in rmunused_module_signals and changes compare_signals ordering for bits on the same wire; may change canonicalization behavior and can lead to non-deterministic or unintended representative choice without a strict weak ordering.
techlibs/common/prep.cc	Adds run("sort") at the end of the prep script coarse stage to preserve deterministic ordering after fast opt.
techlibs/gowin/synth_gowin.cc	Runs sort before the abc/abc9 mapping in map_luts stage to stabilize ordering for mapping.
techlibs/xilinx/synth_xilinx.cc	Adds run("sort") at end of prepare stage to make subsequent mapping passes see stable ordering; removes reliance on opt/clean sorting.

Sequence Diagram

sequenceDiagram
    participant User as User/Script
    participant Pass as ScriptPass/Pass
    participant Design as RTLIL::Design
    participant Module as RTLIL::Module

    User->>Pass: "Invoke prep / synth_*"
    Pass->>Design: "optimize()"
    Note over Pass: "PR removes implicit Design::sort() from opt/opt_clean"

    Pass->>Pass: "run('sort') at key stages"
    Pass->>Design: "sort() (explicit)"

    Pass->>Pass: "run('opt_clean')"
    Pass->>Module: "rmunused_module_signals()"
    Module->>Module: "compare_signals() picks representative"
    Module->>Module: "remove(wires)"
    Note over Module: "remove() returns early on empty pools"

    Pass->>Design: "check()"

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