Presync

Title

PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry

@@ Abstract—@@
Spiking Neural Networks (SNN) have gained relevance in recent times, due to their ability to mimic the biological nature to communicate and process sparse asynchronous binary signals in a massively parallel fashion. SNN based neuromorphic hardware exhibits highly desired favourable properties such as low power consumption, fast inference, and event-driven information processing. A recognized challenge of standard SNN neuron models is their limited capabilities in biological applications, such as applying neural networks to study network responses arising from variations pertaining to damage, external influence or disruptions in channel transfer dynamics.

This paper presents Pre-Synaptic Neuronal Circuit (PreSyNC), a high performance hardware realization of an input-specific presynaptic region of a generic neuron, without abstraction of primary intra-neuronal parameters. PreSyNC is configured to operate on three precision modes: IEEE 754 single precision, double precision and the recently developed universal number posit number system. The developed hardware design is compared to current standards of SNN neuron models as well as biological models in terms of flexibility, resource efficiency and damage modelling capability. Error margins as low as 0.9% were obtained and suggest the capability of our hardware in handling applications involving large scale neuron networks. These architectures are synthesized on 45 nm process
technology where they all operate at a minimum frequency of approximately 1GHz. The three precision modes are compared based on power, accuracy, and sensitivity handling and are expected to benefit implantation oriented applications such as neural prosthesis and Human-Computer Interaction (HMI). The posit-based implementation outperforms the rest of the operating modes in terms of RMS error, while having 26.3% less area and 25.2% less power consumption compared to double precision implementation. These new architectures can be expanded in the future with various post-synaptic inputs to open up a broader understanding of biological systems and other applications.

+ Index Terms—Neuromorphic computation, presynaptic region, neural networks, posit arithmetic

Hardware

• Hardware design of synaptic data-flow accelerator by taking realistic, computationally extensive intra-neuronal parameters in floating point single & double precision & recently developed Posit unum number system (32 bit word with 4 bit exponent size)

• Comparative study in terms of accuracy, precision, sensitivity handling and silicon footprint. The designs are deep pipelined and meets 1Ghz frequency in 45nm ASIC with extensively optimised area and powe

Directory Structure

Directory structure

• .
  • Pre-Print
    • Preprint
  • IEEE_32
    • RTL
      • IEEE32_design.sv
    • Simulation
      • IEEE32_tb.sv
      • result.txt
    • Synthesis_logs
      • area.log
      • power.log
      • powerhier.log
      • timing.log
    • Utility
      • bin_2_dec.cpp
      • run.sh
  • IEEE_64
    • RTL
      • IEEE64_design.sv
    • Simulation
      • IEEE64_tb.sv
      • res_64_dec.csv
    • Synthesis_logs
      • area.log
      • power.log
      • powerhier.log
      • timing.log
    • Utility
      • float64_to_dec.py
      • run.sh
  • Posit_32_4
    • RTL
      • design_posit.sv
    • Simulation
      • log_posit.txt
      • result_decimal.csv
      • testbench_posit.sv
    • Synthesis_logs
      • area.log
      • power.log
      • powerhier.log
      • timing.log
    • Utility
      • posit32hex.py
      • run.sh
  • README.md

Description of contents-

+ RTL - contains design
+ Simulation - contains testbench and decimal results
+ Synthesis_logs - contains synthesis results in Synopsys DC in 45nm ASIC
+ Utility - contains Questasim 10.0b simulator run script and *.py/*.cpp file for conversion of posit<32,4> to decimal & IEEE32,64 to decimal

Instruction to run-

# 1) Run the *.sh script present in Utlity folder. It will compile + simulate RTL+TB and generate log file in Simulation folder. Will run in Windows 32/64 bit OS in batch mode.
! Note- Change the Questasim executables(vlib, vlog, vsim) paths incase of Ubuntu or any Unix system to the respective paths where they get installed.
# 2) Execute the *.py/*.cpp file present in Utility folder to generate .csv or .txt file which will contain converted results from binary/hexadecimal to accurate decimals.  

Copyright & Citations

@inproceedings{2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID),
    title     = {PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry},
    author    = {Rounak Chatterjee; Souradeep Chowdhury; Soham Mondal; Arnab Raha; Janet Paluh; Amitava Mukherjee},
    publisher = {IEEE},
    DOI       = {https://doi.org/10.1109/VLSID51830.2021.00044},
    URL       = {https://ieeexplore.ieee.org/document/9407457},
    year      = {2021}
}