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1. OpenLane-VSD OpenLane-VSD Public

   Have used the PicoRV32 — a small and stable RISC-V core — as our RTL design for this backend flow. Additionally, we will create a standard cell library that will be used to generate the netlist fro…

2. RAM-Verification-SV RAM-Verification-SV Public

   Repo contains a verification environment for a custom 32RAM design using SystemVerilog

   SystemVerilog 1

3. Verilog-CodeGen Verilog-CodeGen Public

   This a mini tool which will generate your desired Verilog Code. Feel free to use and share it with others

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4. AMBA_AHB AMBA_AHB Public

   Single Master Multiple Slave AHB protocol is carried out. Necessary images of architecture used are also attached. Pls check them out!

   Verilog