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Add a documentation for CombInit #228
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Co-authored-by: Andreas Wallner <A.Wallner@innovative-solutions.at>
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@@ -145,7 +145,7 @@ CombInit | |
// At this point c === 1 and d === 2. | ||
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``CombInit`` clones a circuit, and initially drive it with the same input at the cloned value. | ||
``CombInit`` clones a circuit, and initially drive it with the same input as the cloned value. | ||
But you can now update the circuit without impacting the initial value. | ||
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If we look at the resulting Verilog, ``b`` is not present : | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I think this is more a statement about references than There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Yeah, 148 and 149 are a bit redundant with the earlier CombInit description. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Cf 6222df6. |
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We could add an example here for one of the major use-cases which is to make helper functions that break the reference to the original signal. That would explain what to use it for, I found it's pretty rare in "normal" HDL code. A dumb example would be:
where we shouldn't return just
b
in thefalse
case as that would create weird behavior (if true the return value can't influence the original b, if false it can)Do you think that makes sense?
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Thanks for your suggestions.
I like your invertedIf example, I was looking for a simple realistic use case : this is it.
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See 6222df6 for a first try.