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Add a documentation for CombInit #228

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Update source/SpinalHDL/Semantic/assignments.rst
Co-authored-by: Andreas Wallner <A.Wallner@innovative-solutions.at>
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ronan-lashermes and andreasWallner authored Nov 10, 2023
commit 2d2086013ce6b37f4f8ada9601c22c222338b19f
2 changes: 1 addition & 1 deletion source/SpinalHDL/Semantic/assignments.rst
Original file line number Diff line number Diff line change
@@ -145,7 +145,7 @@ CombInit
// At this point c === 1 and d === 2.
}

``CombInit`` clones a circuit, and initially drive it with the same input at the cloned value.
``CombInit`` clones a circuit, and initially drive it with the same input as the cloned value.
But you can now update the circuit without impacting the initial value.

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We could add an example here for one of the major use-cases which is to make helper functions that break the reference to the original signal. That would explain what to use it for, I found it's pretty rare in "normal" HDL code. A dumb example would be:

// note that condition is an elaboration time constant
def invertedIf(b: Bits, condition: Boolean): Bits = if(condition) { ~b } else { CombInit(b) }

where we shouldn't return just b in the false case as that would create weird behavior (if true the return value can't influence the original b, if false it can)
Do you think that makes sense?

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Thanks for your suggestions.
I like your invertedIf example, I was looking for a simple realistic use case : this is it.

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See 6222df6 for a first try.

If we look at the resulting Verilog, ``b`` is not present :
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I think this is more a statement about references than CombInit - but I have no big issue keeping it if you think it helps a bunch.

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Yeah, 148 and 149 are a bit redundant with the earlier CombInit description.
151 was there to insist on the differences in the synthesis results, I would like to keep it but add a bit more contextual description.

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Cf 6222df6.