DHRUT-V

Custom Designed RISC-V core for educational and learning purpose
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Table of Contents

1. About The Project
   • Built With
2. Getting Started
   • Prerequisites
   • Installation
3. Usage
4. Roadmap
5. Contributing
6. License
7. Contact
8. Acknowledgments

About The Project

This is a custom designed RISC-V core, fouced on easy understading of the RISC-V ISA, RISC-V microarchitecture design and verified using open-source and RISC-V tool chains.

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Designed and Verified with

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Getting Started

The project uses riscv-gcc cross-compiler to compile and link the tests. Spike simulator as the Instruction Set Simulator. The verilog files are compiled using iverilog and waveform is run using gtkwave tool. (lint checking and formal verification yet to be added, verilator and symbi-yosys to be used). Makefile has been used to run different tasks and install toolchains.

Install toolchains

make init

Simulating a program on the core and Spike

1. This will take the program as the default program to run on the core

make core

2. To run your own custom program on the core

make core TEST_PROGRAM=<your_test_name>

3. To run a single verilog file(test bench should be in and verilog design should be in

make compile TB=<test_bench_name> DESIGN=<module_name>

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Roadmap

• Pipeline the Core
• Add CSR Features
• Run RISC-V Compitability tests
• Add Coverage Features, Formal Verification and Lint checks
• Synthesize and Run on FPGA

See the open issues for a full list of proposed features (and known issues).

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License

Distributed under the Apache License 2.0. See LICENSE.txt for more information.

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Project Creator

Sudeep Joshi - sudeepj881@gmail.com

Project Link: https://github.com/SudeepJoshi22/DHRUT-V

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Contributors

-

Profile : social handle

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