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ci: add basic ci

ci: add basic ci #1

Triggered via push December 22, 2023 09:24
@Tang-HaojinTang-Haojin
pushed bb7c15c
master
Status Failure
Total duration 4m 51s
Artifacts –

push.yml

on: push
Simulate all tests
4m 39s
Simulate all tests
Matrix: Generate Verilog
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29 errors
Generate Verilog (rv64)
unable to connect to github.com:
Generate Verilog (rv64)
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (rv64)
unable to connect to github.com:
Generate Verilog (rv64)
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (rv64)
Failed to recurse into submodule path 'ysyxSoC/torture'
Generate Verilog (rv64)
Failed to recurse into submodule path 'ysyxSoC'
Generate Verilog (rv64)
The process '/usr/bin/git' failed with exit code 1
Simulate all tests
unable to connect to github.com:
Generate Verilog (lxb)
unable to connect to github.com:
Simulate all tests
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (zmb)
The job was canceled because "rv64" failed.
Generate Verilog (lxb)
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Simulate all tests
unable to connect to github.com:
Generate Verilog (zmb)
unable to connect to github.com:
Generate Verilog (lxb)
unable to connect to github.com:
Simulate all tests
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (lxb)
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (zmb)
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (lxb)
Failed to recurse into submodule path 'ysyxSoC/torture'
Simulate all tests
Failed to recurse into submodule path 'ysyxSoC/torture'
Generate Verilog (zmb)
unable to connect to github.com:
Generate Verilog (lxb)
Failed to recurse into submodule path 'ysyxSoC'
Simulate all tests
Failed to recurse into submodule path 'ysyxSoC'
Generate Verilog (zmb)
clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path '/home/runner/work/YuQuan/YuQuan/ysyxSoC/torture/env' failed
Generate Verilog (lxb)
The process '/usr/bin/git' failed with exit code 1
Generate Verilog (zmb)
Failed to recurse into submodule path 'ysyxSoC/torture'
Simulate all tests
The process '/usr/bin/git' failed with exit code 1
Generate Verilog (zmb)
Failed to recurse into submodule path 'ysyxSoC'
Generate Verilog (zmb)
The process '/usr/bin/git' failed with exit code 1