chore: bump mill 0.11.6, scala 2.13.12 and chisel 6.0.0-RC1

.gitignore

@@ -14,6 +14,5 @@ build/
 *.fst
 *.hier
 .config
-.mill-version
 obj_dir/
 *.log

.mill-version

@@ -0,0 +1 @@
+0.11.6

Makefile

@@ -7,21 +7,15 @@ srcDir    = $(pwd)/cpu/src
 cpuNum    = $(shell echo $$((`lscpu -p=CORE | tail -n 1` + 1)))
 nobin     = $(shell echo "\e[31mNo BIN file specified\e[0m")
 
-# firtool sanity checks
-FIRTOOL := $(shell firtool --version 2>/dev/null)
-ifndef FIRTOOL
-$(error firtool is not available. Please install firtool at https://github.com/llvm/circt/releases)
-endif
-FIRTOOL_HAS_VER := $(shell firtool --version | tail -1 | grep -o 'CIRCT')
-ifndef FIRTOOL_HAS_VER
-$(error firtool < 1.43.0. Please upgrade firtool at https://github.com/llvm/circt/releases)
-endif
-FIRTOOL_VER_MAJOR := $(shell firtool --version | tail -1 | grep -o '[0-9]*' | head -1)
-FIRTOOL_VER_MINOR := $(shell firtool --version | tail -1 | grep -o '[0-9]*' | tail -2 | head -1)
-FIRTOOL_SUCCESS := $(shell ([ $(FIRTOOL_VER_MINOR) -ge 43 ] 2>/dev/null || [ $(FIRTOOL_VER_MAJOR) -gt 1 ] 2>/dev/null) && echo success)
-ifneq ($(FIRTOOL_SUCCESS),success)
-$(error firtool < 1.43.0. Please upgrade firtool at https://github.com/llvm/circt/releases)
+# firtool check and download
+FIRTOOL_VERSION = 1.61.0
+FIRTOOL_URL = https://github.com/llvm/circt/releases/download/firtool-$(FIRTOOL_VERSION)/firrtl-bin-linux-x64.tar.gz
+CACHE_FIRTOOL_PATH = $(HOME)/.cache/yuquan/firtool-$(FIRTOOL_VERSION)/bin/firtool
+ifeq ($(wildcard $(CACHE_FIRTOOL_PATH)),)
+$(info [INFO] Downloading from $(FIRTOOL_URL))
+$(shell mkdir -p $(HOME)/.cache/yuquan && curl -L $(FIRTOOL_URL) | tar -xzC $(HOME)/.cache/yuquan)
 endif
+FIRTOOL_ARGS = --firtool-binary-path $(CACHE_FIRTOOL_PATH)
 
 ISA := riscv64
 
@@ -87,12 +81,12 @@ test:
 	mill -i __.test
 
 verilog:
-	mill -i __.cpu.runMain Elaborate -td $(BUILD_DIR)/cpu $(PRETTY)
+	mill -i cpu.runMain cpu.top.Elaborate -td $(BUILD_DIR)/cpu $(PRETTY) $(FIRTOOL_ARGS)
 	@$(pwd)/tools/split_blackbox.sh $(BUILD_DIR)/cpu ysyx_210153.v
 	@sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $(BUILD_DIR)/cpu/ysyx_210153.v
 
 help:
-	mill -i __.sim.runMain Elaborate --help
+	mill -i sim.runMain sim.top.Elaborate --help
 
 compile:
 	mill -i __.compile
@@ -122,7 +116,7 @@ clean-all: clean
 	-rm -rf ./out ./difftest/build ./difftest/difftest/build
 
 verilate:
-	mill -i __.sim.runMain Elaborate -td $(BUILD_DIR)/sim $(GENNAME) $(param)
+	mill -i sim.runMain sim.top.Elaborate -td $(BUILD_DIR)/sim $(GENNAME) $(param) $(FIRTOOL_ARGS)
 	@$(pwd)/tools/split_blackbox.sh $(BUILD_DIR)/sim TestTop.v
 	@cd $(BUILD_DIR)/sim && \
 	verilator $(VFLAGS) --build $(CSRCS) -CFLAGS "$(CFLAGS)" -LDFLAGS "$(LDFLAGS)" >/dev/null
@@ -141,11 +135,11 @@ simall: $(LIB_SPIKE) verilate
 	done
 
 zmb:
-	mill -i __.cpu.runMain Elaborate -td $(BUILD_DIR)/zmb zmb $(PRETTY)
+	mill -i cpu.runMain cpu.top.Elaborate -td $(BUILD_DIR)/zmb zmb $(PRETTY) $(FIRTOOL_ARGS)
 	@$(pwd)/tools/split_blackbox.sh $(BUILD_DIR)/zmb zmb.v
 
 lxb:
-	mill -i __.cpu.runMain Elaborate -td $(BUILD_DIR)/lxb lxb $(PRETTY)
+	mill -i cpu.runMain cpu.top.Elaborate -td $(BUILD_DIR)/lxb lxb $(PRETTY) $(FIRTOOL_ARGS)
 	@$(pwd)/tools/split_blackbox.sh $(BUILD_DIR)/lxb lxb.v
 
 rv64: verilog

build.sc

@@ -7,18 +7,18 @@ import mill.scalalib.TestModule.Utest
 import mill.bsp._
 
 trait BaseScalaModule extends ScalaModule with ScalafmtModule {
-  override def scalaVersion = "2.13.10"
+  override def scalaVersion = "2.13.12"
   override def scalacOptions = Seq(
     "-language:reflectiveCalls",
     "-deprecation",
     "-feature",
     "-Xcheckinit"
   )
   override def ivyDeps = Agg(
-    ivy"org.chipsalliance::chisel:6.0.0-M2"
+    ivy"org.chipsalliance::chisel:6.0.0-RC1"
   )
   override def scalacPluginIvyDeps = Agg(
-    ivy"org.chipsalliance:::chisel-plugin:6.0.0-M2"
+    ivy"org.chipsalliance:::chisel-plugin:6.0.0-RC1"
   )
 }
 

cpu/src/Elaborate.scala

@@ -1,5 +1,9 @@
+package cpu.top
+
+import chipsalliance.rocketchip.config.Parameters
+
 object Elaborate extends App {
-  implicit private val p = chipsalliance.rocketchip.config.Parameters.empty.alterPartial({ case cpu.GEN_NAME =>
+  implicit private val p: Parameters = Parameters.empty.alterPartial({ case cpu.GEN_NAME =>
     if (args.contains("zmb")) "zmb"
     else if (args.contains("lxb")) "lxb"
     else "ysyx"

cpu/src/component/mmu/la/LAMMU.scala

@@ -11,15 +11,16 @@ import utils._
 
 class LAMMU(implicit p: Parameters) extends AbstractMMU with LACSRsAddr {
   io.csrIO.foreach(_.rcsr := DontCare)
-  private          val crmd    = io.csrIO(0).rdata.asTypeOf(new CRMDBundle);   io.csrIO(0).rcsr := CRMD
-  private          val dmw0    = io.csrIO(1).rdata;                            io.csrIO(1).rcsr := DMW(0)
-  private          val dmw1    = io.csrIO(2).rdata;                            io.csrIO(2).rcsr := DMW(1)
-  private implicit val asid    = io.csrIO(3).rdata.asTypeOf(new ASIDBundle);   io.csrIO(3).rcsr := ASID
-  private          val tlbehi  = io.csrIO(4).rdata;                            io.csrIO(4).rcsr := TLBEHI
-  private          val tlbelo0 = io.csrIO(5).rdata;                            io.csrIO(5).rcsr := TLBELO0
-  private          val tlbelo1 = io.csrIO(6).rdata;                            io.csrIO(6).rcsr := TLBELO1
-  private          val tlbidx  = io.csrIO(7).rdata.asTypeOf(new TLBIDXBundle); io.csrIO(7).rcsr := TLBIDX
-  private          val estat   = io.csrIO(8).rdata.asTypeOf(new ESTATBundle);  io.csrIO(8).rcsr := ESTAT
+  private val crmd    = io.csrIO(0).rdata.asTypeOf(new CRMDBundle);   io.csrIO(0).rcsr := CRMD
+  private val dmw0    = io.csrIO(1).rdata;                            io.csrIO(1).rcsr := DMW(0)
+  private val dmw1    = io.csrIO(2).rdata;                            io.csrIO(2).rcsr := DMW(1)
+  private val asid    = io.csrIO(3).rdata.asTypeOf(new ASIDBundle);   io.csrIO(3).rcsr := ASID
+  private val tlbehi  = io.csrIO(4).rdata;                            io.csrIO(4).rcsr := TLBEHI
+  private val tlbelo0 = io.csrIO(5).rdata;                            io.csrIO(5).rcsr := TLBELO0
+  private val tlbelo1 = io.csrIO(6).rdata;                            io.csrIO(6).rcsr := TLBELO1
+  private val tlbidx  = io.csrIO(7).rdata.asTypeOf(new TLBIDXBundle); io.csrIO(7).rcsr := TLBIDX
+  private val estat   = io.csrIO(8).rdata.asTypeOf(new ESTATBundle);  io.csrIO(8).rcsr := ESTAT
+  private implicit val asidParam: cpu.privileged.ASIDBundle = asid
   private val dmw    = Seq(dmw0, dmw1).map(_.asTypeOf(new DMWBundle))
   private val tlbelo = Seq(tlbelo0,tlbelo1).map(_.asTypeOf(new TLBELOBundle))
   val idle::refilled::Nil = Enum(2)

sim/src/Elaborate.scala

@@ -1,10 +1,14 @@
+package sim.top
+
+import chipsalliance.rocketchip.config.Parameters
+
 object Elaborate extends App {
-  implicit var p = (new sim.SimConfig).alter(cpu.cache.CacheConfig.f).alterPartial({ case cpu.GEN_NAME => if (args.contains("zmb")) "zmb" else "ysyx" })
+  implicit var p: Parameters = (new sim.SimConfig).alter(cpu.cache.CacheConfig.f).alterPartial({ case cpu.GEN_NAME => if (args.contains("zmb")) "zmb" else "ysyx" })
 
   if (args.contains("FLASH")) p = p.alterPartial({ case cpu.USEFLASH => true })
 
   (new circt.stage.ChiselStage).execute(
-    Array("--target", "verilog") ++ args.take(2),
+    Array("--target", "verilog") ++ args,
     Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new sim.cpu.TestTop))
   )
 }

utils/src/PrefixModule.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 import chipsalliance.rocketchip.config._
 
 abstract class PrefixModule(implicit val p: Parameters) extends Module with PrefixParams {
-  implicit val implReset = reset.asBool
+  implicit val implReset: Bool = reset.asBool
 
   implicit class b39ca268[S <: Data, T <: Data](x: (S, T)) {
     def :=(that: (S, T)): Unit = { x._1 := that._1; x._2 := that._2 }