Add hardware verification workflows for Verilog code quality

[Copilot]

Adds automated verification workflows for continuous integration of Verilog code using industry-standard tools.

Workflows Added

• Linting (lint.yml) - Verible static analysis for code quality and style violations
• Simulation (simulation.yml) - Icarus Verilog to detect and report available testbenches
• Verification (verification.yml) - Verilator lint mode with -Wall for comprehensive checking

All workflows:

• Run on push to main and PRs
• Use explicit permissions: contents: read for token security
• Handle multiple .v files across repository structure

Documentation

Updated README to describe all verification workflows (including existing synthesis) with consolidated instructions for viewing results in Actions tab.

Other Changes

• Fixed YAML formatting in existing synthesis.yml for consistency
• All workflows pass yamllint validation

Original prompt

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This section details on the original issue you should resolve

<issue_title>Add hardware verification actions</issue_title>
<issue_description></issue_description>

Comments on the Issue (you are @copilot in this section)

• Fixes Add hardware verification actions #30

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