Merge pull request #6815 from AcKoucher/mpl-orient-fix

mpl: fix orientation improvement and add tests
The-OpenROAD-Project · Mar 5, 2025 · be01bb8 · be01bb8
2 parents 1d7f915 + 97d8303
commit be01bb8
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Showing 10 changed files with 715 additions and 8 deletions.
diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp
@@ -2771,12 +2771,12 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro)
 {
   float wirelength = 0.0f;
 
-  for (odb::dbITerm* iterm : macro->getITerms()) {
-    if (iterm->getSigType() != odb::dbSigType::SIGNAL) {
+  for (odb::dbITerm* macro_pin : macro->getITerms()) {
+    if (macro_pin->getSigType() != odb::dbSigType::SIGNAL) {
       continue;
     }
 
-    odb::dbNet* net = iterm->getNet();
+    odb::dbNet* net = macro_pin->getNet();
     if (net != nullptr) {
       // Mimic dbNet::getTermBBox() behavior, but considering
       // the pin constraint region instead of its position.
@@ -2799,10 +2799,10 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro)
           odb::Rect region_rect(x, y, x, y);
           net_box.merge(region_rect);
         } else {
-          odb::Point bterm_location(bterm->getBBox().xCenter(),
-                                    bterm->getBBox().yCenter());
-          Boundary closest_boundary
-              = getClosestBoundary(bterm_location, tree_->unblocked_boundaries);
+          odb::Point macro_pin_location(macro_pin->getBBox().xCenter(),
+                                        macro_pin->getBBox().yCenter());
+          Boundary closest_boundary = getClosestBoundary(
+              macro_pin_location, tree_->unblocked_boundaries);
 
           // As we classify the blocked/unblocked state of the boundary based on
           // the extension of the -exclude constraint, it's possible to have
@@ -2814,7 +2814,7 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro)
           }
 
           odb::Point closest_point
-              = getClosestBoundaryPoint(bterm_location, closest_boundary);
+              = getClosestBoundaryPoint(macro_pin_location, closest_boundary);
           odb::Rect closest_point_rect(closest_point, closest_point);
           net_box.merge(closest_point_rect);
         }

diff --git a/src/mpl/test/CMakeLists.txt b/src/mpl/test/CMakeLists.txt
@@ -8,6 +8,8 @@ or_integration_tests(
     io_constraints1
     io_constraints2
     io_pads1
+    orientation_improve1
+    orientation_improve2
 )
 
 # Skipped

diff --git a/src/mpl/test/orientation_improve1.defok b/src/mpl/test/orientation_improve1.defok
@@ -0,0 +1,111 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 240000 240000 ) ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 18000 19600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 18000 22400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 18000 25200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 18000 28000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 18000 30800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 18000 33600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 18000 36400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 18000 39200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 18000 42000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 18000 44800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 18000 47600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 18000 50400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 18000 53200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 18000 56000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 18000 58800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 18000 61600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 18000 64400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 18000 67200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 18000 70000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 18000 72800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 18000 75600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 18000 78400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 18000 81200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 18000 84000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 18000 86800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 18000 89600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 18000 92400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 18000 95200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 18000 98000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 18000 100800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 18000 103600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 18000 106400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 18000 109200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 18000 112000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 18000 114800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 18000 117600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 18000 120400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 18000 123200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 18000 126000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 18000 128800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 18000 131600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 18000 134400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 18000 137200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 18000 140000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 18000 142800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 18000 145600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 18000 148400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 18000 151200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 18000 154000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 18000 156800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 18000 159600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 18000 162400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 18000 165200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 18000 168000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 18000 170800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 18000 173600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 18000 176400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 18000 179200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 18000 182000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 18000 184800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 18000 187600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 18000 190400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 18000 193200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 18000 196000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 18000 198800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 18000 201600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 18000 204400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 18000 207200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 18000 210000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 18000 212800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 18000 215600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 18000 218400 N DO 536 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 1 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 21080 21050 ) S ;
+END COMPONENTS
+PINS 1 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER metal5 ( -140 -140 ) ( 140 140 )
+        + PLACED ( 239860 34860 ) N ;
+END PINS
+NETS 1 ;
+    - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/orientation_improve1.ok b/src/mpl/test/orientation_improve1.ok
@@ -0,0 +1,30 @@
+[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: ./testcases/orientation_improve1.lef, created 9 library cells
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 1 components and 2 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 1 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 10.00u-30.00u, in the RIGHT edge.
+Found 1 macro blocks.
+Using 2 tracks default min distance between IO pins.
+[INFO PPL-0001] Number of slots           842
+[INFO PPL-0002] Number of I/O             1
+[INFO PPL-0003] Number of I/O w/sink      1
+[INFO PPL-0004] Number of I/O w/o sink    0
+[INFO PPL-0012] I/O nets HPWL: 102.57 um.
+Die Area: (0.00, 0.00) (120.00, 120.00),  Floorplan Area: (9.00, 9.80) (110.84, 110.60)
+	Number of std cell instances: 0
+	Area of std cell instances: 0.00
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 0.30
+	Halo height: 0.30
+	Area of macros with halos: 10120.36
+	Area of std cell instances + Area of macros: 10000.00
+	Floorplan area: 10265.47
+	Design Utilization: 0.97
+	Floorplan Utilization: 0.00
+	Manufacturing Grid: 10
+
+[WARNING MPL-0025] Design has no standard cells!
+No differences found.
diff --git a/src/mpl/test/orientation_improve1.tcl b/src/mpl/test/orientation_improve1.tcl
@@ -0,0 +1,19 @@
+# Test orientation improvement with one constrained pin.
+source "helpers.tcl"
+
+read_lef "./Nangate45/Nangate45.lef"
+read_lef "./testcases/orientation_improve1.lef"
+
+read_def "./testcases/orientation_improve1.def"
+
+# Run random PPL to incorporate the constraints into ODB
+set_io_pin_constraint -direction INPUT -region right:10-30*
+place_pins -annealing -random -hor_layers metal5 -ver_layer metal6
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/orientation_improve1 -halo_width 0.3
+
+set def_file [make_result_file orientation_improve1.def]
+write_def $def_file
+
+diff_files orientation_improve1.defok $def_file
diff --git a/src/mpl/test/orientation_improve2.defok b/src/mpl/test/orientation_improve2.defok
@@ -0,0 +1,111 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 240000 240000 ) ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 18000 19600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 18000 22400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 18000 25200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 18000 28000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 18000 30800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 18000 33600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 18000 36400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 18000 39200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 18000 42000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 18000 44800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 18000 47600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 18000 50400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 18000 53200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 18000 56000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 18000 58800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 18000 61600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 18000 64400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 18000 67200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 18000 70000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 18000 72800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 18000 75600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 18000 78400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 18000 81200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 18000 84000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 18000 86800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 18000 89600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 18000 92400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 18000 95200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 18000 98000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 18000 100800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 18000 103600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 18000 106400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 18000 109200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 18000 112000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 18000 114800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 18000 117600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 18000 120400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 18000 123200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 18000 126000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 18000 128800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 18000 131600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 18000 134400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 18000 137200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 18000 140000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 18000 142800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 18000 145600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 18000 148400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 18000 151200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 18000 154000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 18000 156800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 18000 159600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 18000 162400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 18000 165200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 18000 168000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 18000 170800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 18000 173600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 18000 176400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 18000 179200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 18000 182000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 18000 184800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 18000 187600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 18000 190400 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 18000 193200 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 18000 196000 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 18000 198800 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 18000 201600 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 18000 204400 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 18000 207200 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 18000 210000 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 18000 212800 N DO 536 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 18000 215600 FS DO 536 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 18000 218400 N DO 536 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 1 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 18600 20490 ) FS ;
+END COMPONENTS
+PINS 1 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER metal5 ( -140 -140 ) ( 140 140 )
+        + PLACED ( 140 154700 ) N ;
+END PINS
+NETS 1 ;
+    - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/orientation_improve2.ok b/src/mpl/test/orientation_improve2.ok
@@ -0,0 +1,29 @@
+[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: ./testcases/orientation_improve1.lef, created 9 library cells
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 1 components and 2 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 1 connections.
+Found 1 macro blocks.
+Using 2 tracks default min distance between IO pins.
+[INFO PPL-0001] Number of slots           842
+[INFO PPL-0002] Number of I/O             1
+[INFO PPL-0003] Number of I/O w/sink      1
+[INFO PPL-0004] Number of I/O w/o sink    0
+[INFO PPL-0012] I/O nets HPWL: 77.35 um.
+Die Area: (0.00, 0.00) (120.00, 120.00),  Floorplan Area: (9.00, 9.80) (110.84, 110.60)
+	Number of std cell instances: 0
+	Area of std cell instances: 0.00
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 0.30
+	Halo height: 0.30
+	Area of macros with halos: 10120.36
+	Area of std cell instances + Area of macros: 10000.00
+	Floorplan area: 10265.47
+	Design Utilization: 0.97
+	Floorplan Utilization: 0.00
+	Manufacturing Grid: 10
+
+[WARNING MPL-0025] Design has no standard cells!
+No differences found.