cts: add recording of masters used to report_cts

src/cts/src/CtsOptions.h

@@ -37,6 +37,7 @@
 
 #include <cstdint>
 #include <iostream>
+#include <map>
 #include <optional>
 #include <sstream>
 #include <string>
@@ -253,6 +254,9 @@ class CtsOptions
   const char* getCtsLibrary() { return ctsLibrary_.c_str(); }
   bool isCtsLibrarySet() { return !ctsLibrary_.empty(); }
 
+  void recordBuffer(odb::dbMaster* master) { buffer_count_[master]++; }
+  std::map<odb::dbMaster*, int> getBufferCount() const { return buffer_count_; }
+
  private:
   std::string clockNets_ = "";
   std::string rootBuffer_ = "";
@@ -311,6 +315,7 @@ class CtsOptions
   bool dummyLoad_ = true;
   float delayBufferDerate_ = 1.0;  // no derate
   std::string ctsLibrary_;
+  std::map<odb::dbMaster*, int> buffer_count_;
 };
 
 }  // namespace cts

src/cts/src/TritonCTS.cpp

@@ -567,23 +567,26 @@ void TritonCTS::reportCtsMetrics()
     file << "Total number of Clock Subnets: " << options_->getNumClockSubnets()
          << ".\n";
     file << "Total number of Sinks: " << options_->getNumSinks() << ".\n";
+
+    file << "Cells used:\n";
+    for (const auto& [master, count] : options_->getBufferCount()) {
+      file << "  " << master->getName() << ": " << count << "\n";
+    }
     file.close();
 
   } else {
-    logger_->info(CTS,
-                  3,
-                  "Total number of Clock Roots: {}.",
-                  options_->getNumClockRoots());
-    logger_->info(CTS,
-                  4,
-                  "Total number of Buffers Inserted: {}.",
-                  options_->getNumBuffersInserted());
-    logger_->info(CTS,
-                  5,
-                  "Total number of Clock Subnets: {}.",
-                  options_->getNumClockSubnets());
-    logger_->info(
-        CTS, 6, "Total number of Sinks: {}.", options_->getNumSinks());
+    logger_->report("Total number of Clock Roots: {}.",
+                    options_->getNumClockRoots());
+    logger_->report("Total number of Buffers Inserted: {}.",
+                    options_->getNumBuffersInserted());
+    logger_->report("Total number of Clock Subnets: {}.",
+                    options_->getNumClockSubnets());
+    logger_->report("Total number of Sinks: {}.", options_->getNumSinks());
+
+    logger_->report("Cells used:");
+    for (const auto& [master, count] : options_->getBufferCount()) {
+      logger_->report("  {}: {}", master->getName(), count);
+    }
   }
 }
 
@@ -1262,6 +1265,7 @@ Clock TritonCTS::forkRegisterClockNetwork(
   odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str());
   topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_"
                   + clockNet.getSdcName();
+  options_->recordBuffer(master);
   odb::dbInst* clockBuf = odb::dbInst::create(
       block_, master, topBufferName.c_str(), false, target_module);
   odb::dbITerm* inputTerm = getFirstInput(clockBuf);
@@ -1611,6 +1615,7 @@ void TritonCTS::createClockBuffers(Clock& clockNet, odb::dbModule* parent)
   unsigned numBuffers = 0;
   clockNet.forEachClockBuffer([&](ClockInst& inst) {
     odb::dbMaster* master = db_->findMaster(inst.getMaster().c_str());
+    options_->recordBuffer(master);
     odb::dbInst* newInst = odb::dbInst::create(
         block_, master, inst.getName().c_str(), false, parent);
     newInst->setSourceType(odb::dbSourceType::TIMING);
@@ -2044,6 +2049,7 @@ ClockInst& TritonCTS::placeDummyCell(Clock& clockNet,
   }
   std::string cellName
       = std::string("clkload") + std::to_string(dummyLoadIndex_++);
+  options_->recordBuffer(master);
   dummyInst = odb::dbInst::create(block_, master, cellName.c_str());
   dummyInst->setSourceType(odb::dbSourceType::TIMING);
   dummyInst->setLocation(inst->getX(), inst->getY());
@@ -2383,6 +2389,7 @@ odb::dbInst* TritonCTS::insertDelayBuffer(odb::dbInst* driver,
   std::string newBufName
       = "delaybuf_" + std::to_string(delayBufIndex_++) + "_" + clockName;
   odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str());
+  options_->recordBuffer(master);
   odb::dbInst* newBuf = odb::dbInst::create(block_, master, newBufName.c_str());
 
   newBuf->setSourceType(odb::dbSourceType::TIMING);

src/cts/test/array.ok

@@ -63,6 +63,16 @@
 [INFO CTS-0101]  Average sink wire length 9259.20 um
 [INFO CTS-0102]  Path depth 18 - 19
 [INFO CTS-0207]  Leaf load cells 62
+Total number of Clock Roots: 1.
+Total number of Buffers Inserted: 231.
+Total number of Clock Subnets: 231.
+Total number of Sinks: 2475.
+Buffers used:
+  BUF_X4: 233
+  INV_X1: 6
+  INV_X16: 6
+  INV_X4: 23
+  INV_X8: 25
 [INFO RSZ-0058] Using max wire length 693um.
 [INFO RSZ-0047] Found 31 long wires.
 [INFO RSZ-0048] Inserted 91 buffers in 31 nets.

src/cts/test/array.tcl

@@ -138,6 +138,8 @@ clock_tree_synthesis  -root_buf $cts_buffer \
     -sink_clustering_max_diameter $cts_cluster_diameter \
     -balance_levels
 
+report_cts
+
 set_propagated_clock [all_clocks]
 estimate_parasitics -placement
 repair_clock_nets

src/cts/test/cts_aux.py

@@ -127,8 +127,10 @@ def clock_tree_synthesis(
 
 
 def report_cts(design, out_file=None):
+    cts = design.getTritonCts()
     if out_file != None:
-        design.getTritonCts.getParms().setMetricsFile(out_file)
+        cts.getParms().setMetricsFile(out_file)
+    cts.reportCtsMetrics()
 
 
 def is_pos_int(x):

src/cts/test/simple_test.ok

@@ -42,4 +42,10 @@
 [INFO CTS-0101]  Average sink wire length 18.87 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 0
+Total number of Clock Roots: 1.
+Total number of Buffers Inserted: 3.
+Total number of Clock Subnets: 3.
+Total number of Sinks: 16.
+Buffers used:
+  CLKBUF_X3: 3
 No differences found.

src/cts/test/simple_test.py

@@ -20,6 +20,8 @@
     apply_ndr=True,
 )
 
+cts_aux.report_cts(design)
+
 def_file = helpers.make_result_file("simple_test_out.def")
 design.writeDef(def_file)
 helpers.diff_files(def_file, "simple_test_out.defok")

src/cts/test/simple_test.tcl

@@ -10,9 +10,10 @@ set_wire_rc -clock -layer metal3
 clock_tree_synthesis -root_buf CLKBUF_X3 \
                      -buf_list CLKBUF_X3 \
                      -wire_unit 20 \
-                     -apply_ndr    
+                     -apply_ndr
+
+report_cts
 
 set def_file [make_result_file simple_test_out.def]
 write_def $def_file
 diff_files simple_test_out.defok $def_file
-

src/cts/test/simple_test_clustered.ok

@@ -46,3 +46,9 @@
 [INFO CTS-0101]  Average sink wire length 125.99 um
 [INFO CTS-0102]  Path depth 2 - 3
 [INFO CTS-0207]  Leaf load cells 2
+Total number of Clock Roots: 1.
+Total number of Buffers Inserted: 35.
+Total number of Clock Subnets: 35.
+Total number of Sinks: 300.
+Buffers used:
+  CLKBUF_X3: 37

src/cts/test/simple_test_clustered.py

@@ -25,3 +25,5 @@
     sink_clustering_max_diameter=60.0,
     num_static_layers=1,
 )
+
+cts_aux.report_cts(design)

src/cts/test/simple_test_clustered.tcl

@@ -19,3 +19,5 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \
                      -sink_clustering_size 10 \
                      -sink_clustering_max_diameter 60 \
                      -num_static_layers 1
+
+report_cts