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Release version 0.33
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mmicko committed Sep 5, 2023
1 parent b75959f commit 2584903
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12 changes: 11 additions & 1 deletion CHANGELOG
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Expand Up @@ -2,8 +2,18 @@
List of major changes and improvements between releases
=======================================================

Yosys 0.32 .. Yosys 0.33-dev
Yosys 0.32 .. Yosys 0.33
--------------------------
* Various
- Added "$print" cell, produced by "$display" and "$write"
Verilog tasks.
- Added "$print" cell handling in CXXRTL.

* Lattice FPGA support
- Added generic "synth_lattice" pass (for now MachXO2/XO3/XO3D)
- Removed "synth_machxo2" pass
- Pass "ecp5_gsr" renamed to "lattice_gsr"
- "synth_machxo2" equivalent is "synth_lattice -family xo2"

Yosys 0.31 .. Yosys 0.32
--------------------------
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4 changes: 2 additions & 2 deletions Makefile
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Expand Up @@ -141,7 +141,7 @@ LDLIBS += -lrt
endif
endif

YOSYS_VER := 0.32+79
YOSYS_VER := 0.33

# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
Expand All @@ -157,7 +157,7 @@ endif
OBJS = kernel/version_$(GIT_REV).o

bumpversion:
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline fbab08a.. | wc -l`/;" Makefile
# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline fbab08a.. | wc -l`/;" Makefile

# set 'ABCREV = default' to use abc/ as it is
#
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