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feat: update project tt_um_spiff42_exp_led_pwm from spiff42/tt06-exp-…
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…led-pwm

Commit: 17e882d06a1ede26ae933e6653011f8f31b980ba
Workflow: https://github.com/spiff42/tt06-exp-led-pwm/actions/runs/8758125772
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Apr 19, 2024
1 parent 072116c commit fb1c616
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Showing 7 changed files with 37,558 additions and 35,704 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_spiff42_exp_led_pwm/commit_id.json
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{
"app": "Tiny Tapeout tt06 7f56a586",
"repo": "https://github.com/spiff42/tt06-exp-led-pwm",
"commit": "a9471eb2c55a200976bccd9bde5481183ce993c7",
"workflow_url": "https://github.com/spiff42/tt06-exp-led-pwm/actions/runs/8755790858",
"commit": "17e882d06a1ede26ae933e6653011f8f31b980ba",
"workflow_url": "https://github.com/spiff42/tt06-exp-led-pwm/actions/runs/8758125772",
"sort_id": 1712340292807,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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2 changes: 1 addition & 1 deletion projects/tt_um_spiff42_exp_led_pwm/stats/metrics.csv
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@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_spiff42_exp_led_pwm,wokwi,flow completed,0h2m42s0ms,0h2m17s0ms,95573.75442223549,0.01795472,47786.877211117746,52.17,53.990300000000005,552.52,771,0,0,0,0,0,0,0,0,0,0,-1,-1,21060,6266,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,14082923.0,0.0,44.84,32.1,8.92,3.08,-1,1323,1661,66,343,0,0,0,1416,59,24,37,71,364,78,22,73,140,131,10,732,225,1,347,858,2163,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_spiff42_exp_led_pwm,wokwi,flow completed,0h2m49s0ms,0h2m25s0ms,97021.84161045117,0.01795472,48510.920805225585,53.73,54.6806,554.77,800,0,0,0,0,0,0,0,0,0,0,-1,-1,22038,6619,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,14895614.0,0.0,45.78,34.77,7.49,3.48,-1,1387,1725,66,343,0,0,0,1480,75,24,61,63,380,62,38,73,140,131,10,724,225,0,353,871,2173,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
105 changes: 52 additions & 53 deletions projects/tt_um_spiff42_exp_led_pwm/stats/synthesis-stats.txt
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Expand Up @@ -3,74 +3,73 @@

=== tt_um_spiff42_exp_led_pwm ===

Number of wires: 755
Number of wire bits: 790
Number of wires: 784
Number of wire bits: 819
Number of public wires: 129
Number of public wire bits: 164
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 771
sky130_fd_sc_hd__a2111o_2 1
sky130_fd_sc_hd__a211o_2 9
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a21bo_2 2
sky130_fd_sc_hd__a21o_2 19
sky130_fd_sc_hd__a21oi_2 23
sky130_fd_sc_hd__a221o_2 20
sky130_fd_sc_hd__a22o_2 46
sky130_fd_sc_hd__a22oi_2 1
sky130_fd_sc_hd__a2bb2o_2 1
sky130_fd_sc_hd__a311o_2 1
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 4
sky130_fd_sc_hd__a31oi_2 1
sky130_fd_sc_hd__a32o_2 7
sky130_fd_sc_hd__a32oi_2 1
sky130_fd_sc_hd__a41o_2 3
sky130_fd_sc_hd__and2_2 11
sky130_fd_sc_hd__and2b_2 5
sky130_fd_sc_hd__and3_2 16
Number of cells: 800
sky130_fd_sc_hd__a211o_2 14
sky130_fd_sc_hd__a211oi_2 2
sky130_fd_sc_hd__a21bo_2 5
sky130_fd_sc_hd__a21o_2 16
sky130_fd_sc_hd__a21oi_2 15
sky130_fd_sc_hd__a221o_2 10
sky130_fd_sc_hd__a22o_2 60
sky130_fd_sc_hd__a2bb2o_2 4
sky130_fd_sc_hd__a311o_2 2
sky130_fd_sc_hd__a31o_2 13
sky130_fd_sc_hd__a32o_2 5
sky130_fd_sc_hd__a41o_2 11
sky130_fd_sc_hd__and2_2 12
sky130_fd_sc_hd__and2b_2 6
sky130_fd_sc_hd__and3_2 24
sky130_fd_sc_hd__and3b_2 2
sky130_fd_sc_hd__and4_2 3
sky130_fd_sc_hd__and4b_2 3
sky130_fd_sc_hd__and4bb_2 2
sky130_fd_sc_hd__buf_1 111
sky130_fd_sc_hd__and4_2 10
sky130_fd_sc_hd__and4b_2 2
sky130_fd_sc_hd__and4bb_2 1
sky130_fd_sc_hd__buf_1 122
sky130_fd_sc_hd__buf_2 9
sky130_fd_sc_hd__conb_1 15
sky130_fd_sc_hd__dfrtp_2 55
sky130_fd_sc_hd__dfxtp_2 76
sky130_fd_sc_hd__inv_2 26
sky130_fd_sc_hd__mux2_2 90
sky130_fd_sc_hd__nand2_2 17
sky130_fd_sc_hd__nand3_2 1
sky130_fd_sc_hd__nand3b_2 2
sky130_fd_sc_hd__nor2_2 28
sky130_fd_sc_hd__nor2b_2 1
sky130_fd_sc_hd__nor3_2 8
sky130_fd_sc_hd__inv_2 24
sky130_fd_sc_hd__mux2_2 86
sky130_fd_sc_hd__nand2_2 15
sky130_fd_sc_hd__nand3_2 3
sky130_fd_sc_hd__nand3b_2 1
sky130_fd_sc_hd__nand4_2 1
sky130_fd_sc_hd__nand4b_2 2
sky130_fd_sc_hd__nor2_2 23
sky130_fd_sc_hd__nor3_2 5
sky130_fd_sc_hd__nor3b_2 3
sky130_fd_sc_hd__nor4b_2 1
sky130_fd_sc_hd__o2111a_2 1
sky130_fd_sc_hd__o211a_2 13
sky130_fd_sc_hd__o2111a_2 2
sky130_fd_sc_hd__o211a_2 4
sky130_fd_sc_hd__o211ai_2 1
sky130_fd_sc_hd__o21a_2 9
sky130_fd_sc_hd__o21ai_2 10
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__o21bai_2 3
sky130_fd_sc_hd__o21a_2 15
sky130_fd_sc_hd__o21ai_2 4
sky130_fd_sc_hd__o21ba_2 6
sky130_fd_sc_hd__o21bai_2 1
sky130_fd_sc_hd__o221a_2 14
sky130_fd_sc_hd__o22a_2 20
sky130_fd_sc_hd__o2bb2a_2 1
sky130_fd_sc_hd__o31a_2 2
sky130_fd_sc_hd__o41a_2 2
sky130_fd_sc_hd__or2_2 23
sky130_fd_sc_hd__or2b_2 4
sky130_fd_sc_hd__o221ai_2 1
sky130_fd_sc_hd__o22a_2 19
sky130_fd_sc_hd__o22ai_2 2
sky130_fd_sc_hd__o2bb2a_2 4
sky130_fd_sc_hd__o311a_2 3
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__o41a_2 1
sky130_fd_sc_hd__or2_2 21
sky130_fd_sc_hd__or2b_2 6
sky130_fd_sc_hd__or3_2 6
sky130_fd_sc_hd__or3b_2 7
sky130_fd_sc_hd__or4_2 12
sky130_fd_sc_hd__or4b_2 6
sky130_fd_sc_hd__or3b_2 11
sky130_fd_sc_hd__or4_2 8
sky130_fd_sc_hd__or4b_2 5
sky130_fd_sc_hd__or4bb_2 1
sky130_fd_sc_hd__xnor2_2 8
sky130_fd_sc_hd__xor2_2 1
sky130_fd_sc_hd__xnor2_2 5
sky130_fd_sc_hd__xor2_2 4

Chip area for module '\tt_um_spiff42_exp_led_pwm': 8305.465600
Chip area for module '\tt_um_spiff42_exp_led_pwm': 8553.203200

Binary file modified projects/tt_um_spiff42_exp_led_pwm/tt_um_spiff42_exp_led_pwm.gds
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20 changes: 10 additions & 10 deletions projects/tt_um_spiff42_exp_led_pwm/tt_um_spiff42_exp_led_pwm.lef
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Expand Up @@ -388,7 +388,7 @@ MACRO tt_um_spiff42_exp_led_pwm
PIN uo_out[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 70.230 110.520 70.530 111.520 ;
Expand Down Expand Up @@ -437,7 +437,7 @@ MACRO tt_um_spiff42_exp_led_pwm
LAYER li1 ;
RECT 2.760 2.635 158.240 108.885 ;
LAYER met1 ;
RECT 2.760 2.480 159.040 109.780 ;
RECT 2.760 2.480 159.040 109.040 ;
LAYER met2 ;
RECT 4.230 2.535 159.010 110.005 ;
LAYER met3 ;
Expand Down Expand Up @@ -485,14 +485,14 @@ MACRO tt_um_spiff42_exp_led_pwm
RECT 148.210 110.120 150.790 111.170 ;
RECT 151.890 110.120 154.470 111.170 ;
RECT 3.975 109.440 155.185 110.120 ;
RECT 3.975 40.295 20.995 109.440 ;
RECT 23.395 40.295 40.430 109.440 ;
RECT 42.830 40.295 59.865 109.440 ;
RECT 62.265 40.295 79.300 109.440 ;
RECT 81.700 40.295 98.735 109.440 ;
RECT 101.135 40.295 118.170 109.440 ;
RECT 120.570 40.295 137.605 109.440 ;
RECT 140.005 40.295 155.185 109.440 ;
RECT 3.975 19.895 20.995 109.440 ;
RECT 23.395 19.895 40.430 109.440 ;
RECT 42.830 19.895 59.865 109.440 ;
RECT 62.265 19.895 79.300 109.440 ;
RECT 81.700 19.895 98.735 109.440 ;
RECT 101.135 19.895 118.170 109.440 ;
RECT 120.570 19.895 137.605 109.440 ;
RECT 140.005 19.895 155.185 109.440 ;
END
END tt_um_spiff42_exp_led_pwm
END LIBRARY
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