Clarify swapping in spice tutorial

spice.md

@@ -163,7 +163,7 @@ M3 3 2 1 0 PCH <parameters such as L=50n W=180n>
 ```
 Note that the connections in the MOSFET are given in the order: drain,
 gate, source, and body. Since MOSFETs are generally symmetric, you can
-usually swap the drain and source.
+usually swap the drain and source. So in this case, you can swap 3 and 1.
 
 ### Instances (X cards)
 

spice/eren/example.sp

@@ -0,0 +1,73 @@
+* Example Inverter with Transient Analysis and Measure
+
+* include the MOSFET models with TT proccess 
+*.lib '~/.volare/sky130A/libs.tech/ngspice/sky130.lib.spice' tt
+
+* include the standard cell library
+*.include '~/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice'
+
+* our supplies are global to the hierarchy
+*.global vdd gnd
+.param supply_voltage=1.8V
+
+* set the operating temperature
+.option temp=27
+
+* include the circuit to be simulated
+*Xinv A gnd gnd vdd vdd IN sky130_fd_sc_hd__inv_1
+
+* If multi-input gate
+*Xnand A B gnd gnd vdd vdd IN sky130_fd_sc_hd__nand2_1
+*V0 B 0 1.8V
+
+* create a voltage pulse on the input
+VSW A 0 PULSE (0V supply_voltage 500ps 5ps 5ps 1000p 2000ps) DC 0V
+Rd A IN 1
+
+* Assume the input is "IN"
+*.include "rc.sp"
+*IN  - R0 - Z1
+*   |- R2 - Z2
+R0 IN n1 1
+C0 n1 gnd 1f
+R1 n1 Z1 1
+C1 Z1 gnd 1f
+R2 n1 Z2 1
+C2 Z2 gnd 1f
+* OR
+*.include "lumped.sp"
+* Start with 0 and Ctotal
+Ceff IN 0 1f
+
+* fanout 4 capacitive load on inverter output
+*Xinv1 Z gnd gnd vdd vdd Z1 sky130_fd_sc_hd__inv_1
+*Xinv2 Z gnd gnd vdd vdd Z2 sky130_fd_sc_hd__inv_1
+*Xinv3 Z gnd gnd vdd vdd Z3 sky130_fd_sc_hd__inv_1
+*Xinv4 Z gnd gnd vdd vdd Z4 sky130_fd_sc_hd__inv_1
+
+* define the supply voltages
+VDD vdd 0 supply_voltage
+*VSS gnd 0 0V
+
+
+* perform a 3ns transient analysis
+.tran 1ps 3ns
+
+.param half_supply = '0.5*supply_voltage'
+.param slew_low = '0.1*supply_voltage'
+.param slew_high = '0.9*supply_voltage'
+
+* measure the input rise to output fall delay 
+* uses a calculation to compute half of 50% of the supply voltage
+.meas tran rise_delay trig v(A) val=half_supply rise=1 targ v(IN) val=half_supply rise=1
+* measure the output rise time (slew)
+*.meas tran rise_time trig v(IN) val=slew_low rise=1 targ v(IN) val=slew_high rise=1
+
+.control
+run
+quit
+* set output file
+* plot A IN
+.endc
+
+.END

spice/eren/lumped.sp

@@ -0,0 +1,2 @@
+* Lumped cap
+