This is a simulation to mimic the memory system hierarchy (L1 cache, L2 cache and DRAM) in a multicore processor. It also deals with how the requests are handled when it hits or misses the cache.
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VimalanKM/Chip-Multi-Processors-Memory-System-Advanced-Cache-DRAM-Design-for-Multicore-Processors
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This is a simulation of multicore processor where a memory system with L1 cache, L2 cache and DRAM has been implemented.
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