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Update video.rst spell error (#1458)
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Fix spelling error in pixel clock description

Corrected "fo" to "for" in the description of the 148.5 MHz pixel clock for 1080p60 video.
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Xilover authored Aug 26, 2024
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Expand Up @@ -99,7 +99,7 @@ flexibility to use the video subsystem color space conversion blocks before and
after the custom IP.

The video pipelines of the Pynq-Z1 and Pynq-Z2 boards run at 142 MHz with one
pixel-per-clock, slightly below the 148.5 MHz pixel clock fo 1080p60 video but
pixel-per-clock, slightly below the 148.5 MHz pixel clock for 1080p60 video but
sufficient once blanking intervals are taken into account. for the ZCU104 board
the pipeline runs at 300 MHz and two pixels-per-clock to support 4k60 (2160p)
video.
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