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Please Add MyIR z-turn #663

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141 changes: 141 additions & 0 deletions boards/Myir/zturn-7z020/2.1/board.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!--
################################################################################
#
# MYiR Z-turn Board Definition File
#
# Sergiusz 'q3k' Bazański <q3k@q3k.org>
# Steffen 'stv0g' Vogel <stv0g@0l.de>
#
################################################################################-->

<board name="mys-7z020" schema_version="2.1" vendor="myir.com" display_name="Z-turn Board (MYS-7Z020-C)" url="http://www.myirtech.com/list.asp?id=502" preset_file="preset.xml">
<images>
<image name="zturn_board.jpg" display_name="Z-turn Board" sub_type="board">
<description>Z-turn Board top image</description>
</image>
</images>
<description>The Z-turn board is a cheap Zynq evaluation board from the Chinese company MYiR Technologies.</description>
<file_version>2.1</file_version>
<compatible_board_revisions>
<revision id="0">4</revision>
</compatible_board_revisions>
<components>
<component name="part0" display_name="Z-turn Board" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.myirtech.com/list.asp?id=502">
<description>FPGA part on the board</description>
<interfaces>
<interface name="ps7_fixedio" mode="master" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset" />
<interface name="rgb_led" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
<preferred_ips>
<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" />
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgb_led_tri_o_0" />
<pin_map port_index="1" component_pin="rgb_led_tri_o_1" />
<pin_map port_index="2" component_pin="rgb_led_tri_o_2" />
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface name="buzzer" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="buzzer" preset_proc="buzzer_preset">
<preferred_ips>
<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" />
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="buzzer_tri_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="buzzer_tri_o_0" />
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface name="sws_4bits" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="sws_4bits_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" />
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="sws_4bits_tri_i_0" />
<pin_map port_index="1" component_pin="sws_4bits_tri_i_1" />
<pin_map port_index="2" component_pin="sws_4bits_tri_i_2" />
<pin_map port_index="3" component_pin="sws_4bits_tri_i_3" />
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="i2c0" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c0">
<description>I2C Interface for onboard G-rate and temperature sensors</description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0" />
</preferred_ips>
<port_maps>
<port_map logical_port="SDA_I" physical_port="i2c0_sda_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="i2c0_sda_i" />
</pin_maps>
</port_map>
<port_map logical_port="SDA_O" physical_port="i2c0_sda_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c0_sda_i" />
</pin_maps>
</port_map>
<port_map logical_port="SDA_T" physical_port="i2c0_sda_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c0_sda_i" />
</pin_maps>
</port_map>
<port_map logical_port="SCL_I" physical_port="i2c0_scl_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="i2c0_scl_i" />
</pin_maps>
</port_map>
<port_map logical_port="SCL_O" physical_port="i2c0_scl_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c0_scl_i" />
</pin_maps>
</port_map>
<port_map logical_port="SCL_T" physical_port="i2c0_scl_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c0_scl_i" />
</pin_maps>
</port_map>
</port_maps>
</interface>
</interfaces>
</component>
<component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group="" />
<component name="buzzer" display_name="Piezo Buzzer" type="chip" sub_type="led" major_group="General Purpose Input or Output">
<description>Piezo Buzzer on Board (Schematic: M1)</description>
</component>
<component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="General Purpose Input or Output">
<description>RGB LED, 2 to 0, Active Low (Schematic: D34)</description>
</component>
<component name="sws_4bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output">
<description>DIP Switches, 3 to 0 (Schematic: U20)</description>
</component>
<component name="i2c0" display_name="IIC" type="chip" sub_type="mux" major_group="Miscellaneous">
<description>I2C Bus 0 wired to PL</description>
</component>
</components>
<jtag_chains>
<jtag_chain name="chain1">
<position name="0" component="part0" />
</jtag_chain>
</jtag_chains>
<connections>
<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
<connection_map name="part0_rgb_led_1" c1_st_index="4" c1_end_index="6" c2_st_index="0" c2_end_index="2" />
</connection>
<connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
<connection_map name="part0_sws_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3" />
</connection>
<connection name="part0_buzzer" component1="part0" component2="buzzer">
<connection_map name="part0_buzzer_1" c1_st_index="7" c1_end_index="7" c2_st_index="0" c2_end_index="0" />
</connection>
<connection name="part0_i2c0" component1="part0" component2="i2c0">
<connection_map name="part0_i2c0_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1" />
</connection>
</connections>
</board>
26 changes: 26 additions & 0 deletions boards/Myir/zturn-7z020/2.1/part0_pins.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?><!--
################################################################################
#
# MYiR Z-turn FPGA Pin Definition File
#
# Sergiusz 'q3k' Bazański <q3k@q3k.org>
# Steffen 'stv0g' Vogel <stv0g@0l.de>
#
################################################################################-->

<part_info part_name="xc7z020clg400-1">
<pins>
<pin index="0" name="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="R19" /><!-- IO_B34_0 -->
<pin index="1" name="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="T19" /><!-- IO_B34_25 -->
<pin index="2" name="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="G14" /><!-- IO_B35_0 -->
<pin index="3" name="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="J15" /><!-- IO_B35_25 -->
<pin index="4" name="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="R14" /><!-- IO_B34_LN6 -->
<pin index="5" name="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="Y16" /><!-- IO_B34_LP7 -->
<pin index="6" name="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="Y17" /><!-- IO_B34_LN7 -->
<pin index="7" name="buzzer_tri_o_0" iostandard="LVCMOS33" loc="P18" /><!-- BP -->
<pin index="8" name ="i2c0_scl_i" iostandard="LVCMOS33" loc="P16" /><!-- I2C0_SCL -->
<pin index="9" name ="i2c0_sda_i" iostandard="LVCMOS33" loc="P15" /><!-- I2C0_SDA -->
<pin index="10" name="mems_temp_intn" iostandard="LVCMOS33" loc="N17" /><!-- MEMS_INTn (wired-or for LM75 and Sil902x)-->
<pin index="11" name="hdmi_int" iostandard="LVCMOS33" loc="W19" /><!-- HDMI_INT -->
</pins>
</part_info>
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