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Xuxingliang
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| Obj/ | ||
| *.o | ||
| *.map | ||
| *.lst | ||
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Submodule ulog-noos
updated
from 370a4d to 998376
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| // ********************************************************************** | ||
| // * SEGGER Microcontroller GmbH * | ||
| // * The Embedded Experts * | ||
| // ********************************************************************** | ||
| // * * | ||
| // * (c) 2014 - 2019 SEGGER Microcontroller GmbH * | ||
| // * (c) 2001 - 2019 Rowley Associates Limited * | ||
| // * * | ||
| // * www.segger.com Support: support@segger.com * | ||
| // * * | ||
| // ********************************************************************** | ||
| // * * | ||
| // * All rights reserved. * | ||
| // * * | ||
| // * Redistribution and use in source and binary forms, with or * | ||
| // * without modification, are permitted provided that the following * | ||
| // * conditions are met: * | ||
| // * * | ||
| // * - Redistributions of source code must retain the above copyright * | ||
| // * notice, this list of conditions and the following disclaimer. * | ||
| // * * | ||
| // * - Neither the name of SEGGER Microcontroller GmbH * | ||
| // * nor the names of its contributors may be used to endorse or * | ||
| // * promote products derived from this software without specific * | ||
| // * prior written permission. * | ||
| // * * | ||
| // * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * | ||
| // * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * | ||
| // * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * | ||
| // * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * | ||
| // * DISCLAIMED. * | ||
| // * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * | ||
| // * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * | ||
| // * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * | ||
| // * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * | ||
| // * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * | ||
| // * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * | ||
| // * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * | ||
| // * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * | ||
| // * DAMAGE. * | ||
| // * * | ||
| // ********************************************************************** | ||
|
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| define memory with size = 4G; | ||
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| // | ||
| // Combined regions per memory type | ||
| // | ||
| define region FLASH = FLASH1; | ||
| define region RAM = RAM1; | ||
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| // | ||
| // Block definitions | ||
| // | ||
| define block ushtable { section ushtable }; // Vector table section | ||
| define block vectors { section .vectors }; // Vector table section | ||
| define block vectors_ram { section .vectors_ram }; // Vector table section | ||
| define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; | ||
| define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; | ||
| define block exidx { section .ARM.exidx, section .ARM.exidx.* }; | ||
| define block tbss { section .tbss, section .tbss.* }; | ||
| define block tdata { section .tdata, section .tdata.* }; | ||
| define block tls { block tbss, block tdata }; | ||
| define block tdata_load { copy of block tdata }; | ||
| define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; | ||
| define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; | ||
| // | ||
| // Explicit initialization settings for sections | ||
| // | ||
| do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; | ||
| initialize by copy /* with packing=auto */ { section .data, section .data.*, section .*.data, section .*.data.* }; | ||
| initialize by copy /* with packing=auto */ { section .fast, section .fast.* }; | ||
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| // | ||
| // Explicit placement in FLASHn | ||
| // | ||
| place in FLASH1 { section .FLASH1, section .FLASH1.* }; | ||
| // | ||
| // FLASH Placement | ||
| // | ||
| place at start of FLASH { block vectors }; // Vector table section | ||
| place in FLASH with minimum size order { section .init, section .init.*, // Init code section | ||
| section .init_rodata, section .init_rodata.*, // Init read-only section | ||
| section .text, section .text.*, // Code section | ||
| section .rodata, section .rodata.*, // Read-only data section | ||
| section .segger.*, // Auto-generated initialization | ||
| block ushtable, // ush table | ||
| block exidx, // ARM exception unwinding block | ||
| block ctors, // Constructors block | ||
| block dtors }; // Destructors block | ||
| place in FLASH { block tdata_load }; // Thread-local-storage load image | ||
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| // | ||
| // Explicit placement in RAMn | ||
| // | ||
| place in RAM1 { section .RAM1, section .RAM1.* }; | ||
| // | ||
| // RAM Placement | ||
| // | ||
| place at start of RAM { block vectors_ram }; | ||
| place in RAM { section .non_init, section .non_init.*, // No initialization section | ||
| block tls }; // Thread-local-storage block | ||
| place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section | ||
| section .data, section .data.*, // Initialized data section | ||
| section .bss, section .bss.* | ||
| }; // Static data section | ||
| place in RAM { block heap }; // Heap reserved block | ||
| place at end of RAM { block stack }; // Stack reserved block at the end | ||
| keep { section ushtable}; |
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| Original file line number | Diff line number | Diff line change |
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| // ********************************************************************** | ||
| // * SEGGER Microcontroller GmbH * | ||
| // * The Embedded Experts * | ||
| // ********************************************************************** | ||
| // * * | ||
| // * (c) 2014 - 2019 SEGGER Microcontroller GmbH * | ||
| // * (c) 2001 - 2019 Rowley Associates Limited * | ||
| // * * | ||
| // * www.segger.com Support: support@segger.com * | ||
| // * * | ||
| // ********************************************************************** | ||
| // * * | ||
| // * All rights reserved. * | ||
| // * * | ||
| // * Redistribution and use in source and binary forms, with or * | ||
| // * without modification, are permitted provided that the following * | ||
| // * conditions are met: * | ||
| // * * | ||
| // * - Redistributions of source code must retain the above copyright * | ||
| // * notice, this list of conditions and the following disclaimer. * | ||
| // * * | ||
| // * - Neither the name of SEGGER Microcontroller GmbH * | ||
| // * nor the names of its contributors may be used to endorse or * | ||
| // * promote products derived from this software without specific * | ||
| // * prior written permission. * | ||
| // * * | ||
| // * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * | ||
| // * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * | ||
| // * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * | ||
| // * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * | ||
| // * DISCLAIMED. * | ||
| // * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * | ||
| // * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * | ||
| // * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * | ||
| // * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * | ||
| // * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * | ||
| // * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * | ||
| // * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * | ||
| // * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * | ||
| // * DAMAGE. * | ||
| // * * | ||
| // ********************************************************************** | ||
|
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| .macro ISR_HANDLER name= | ||
| .section .vectors, "ax" | ||
| .word \name | ||
| .section .init, "ax" | ||
| .thumb_func | ||
| .weak \name | ||
| \name: | ||
| 1: b 1b /* endless loop */ | ||
| .endm | ||
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| .macro ISR_RESERVED | ||
| .section .vectors, "ax" | ||
| .word 0 | ||
| .endm | ||
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| .syntax unified | ||
| .global reset_handler | ||
| .global Reset_Handler | ||
| .equ Reset_Handler, reset_handler | ||
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| .section .vectors, "ax" | ||
| .code 16 | ||
| .balign 2 | ||
| .global _vectors | ||
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| .macro DEFAULT_ISR_HANDLER name= | ||
| .thumb_func | ||
| .weak \name | ||
| \name: | ||
| 1: b 1b /* endless loop */ | ||
| .endm | ||
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| _vectors: | ||
| .word __stack_end__ | ||
| .word reset_handler | ||
| ISR_HANDLER NMI_Handler | ||
| ISR_HANDLER HardFault_Handler | ||
| ISR_HANDLER MemManage_Handler | ||
| ISR_HANDLER BusFault_Handler | ||
| ISR_HANDLER UsageFault_Handler | ||
| ISR_RESERVED | ||
| ISR_RESERVED | ||
| ISR_RESERVED | ||
| ISR_RESERVED | ||
| ISR_HANDLER SVC_Handler | ||
| ISR_HANDLER DebugMon_Handler | ||
| ISR_RESERVED | ||
| ISR_HANDLER PendSV_Handler | ||
| ISR_HANDLER SysTick_Handler | ||
| #ifdef __VECTORS | ||
| #include __VECTORS | ||
| #else | ||
| ISR_HANDLER ExternalISR0 | ||
| ISR_HANDLER ExternalISR1 | ||
| ISR_HANDLER ExternalISR2 | ||
| ISR_HANDLER ExternalISR3 | ||
| ISR_HANDLER ExternalISR4 | ||
| ISR_HANDLER ExternalISR5 | ||
| ISR_HANDLER ExternalISR6 | ||
| ISR_HANDLER ExternalISR7 | ||
| ISR_HANDLER ExternalISR8 | ||
| ISR_HANDLER ExternalISR9 | ||
| ISR_HANDLER ExternalISR10 | ||
| ISR_HANDLER ExternalISR11 | ||
| ISR_HANDLER ExternalISR12 | ||
| ISR_HANDLER ExternalISR13 | ||
| ISR_HANDLER ExternalISR14 | ||
| ISR_HANDLER ExternalISR15 | ||
| ISR_HANDLER ExternalISR16 | ||
| ISR_HANDLER ExternalISR17 | ||
| ISR_HANDLER ExternalISR18 | ||
| ISR_HANDLER ExternalISR19 | ||
| ISR_HANDLER ExternalISR20 | ||
| ISR_HANDLER ExternalISR21 | ||
| ISR_HANDLER ExternalISR22 | ||
| ISR_HANDLER ExternalISR23 | ||
| ISR_HANDLER ExternalISR24 | ||
| ISR_HANDLER ExternalISR25 | ||
| ISR_HANDLER ExternalISR26 | ||
| ISR_HANDLER ExternalISR27 | ||
| ISR_HANDLER ExternalISR28 | ||
| ISR_HANDLER ExternalISR29 | ||
| ISR_HANDLER ExternalISR30 | ||
| ISR_HANDLER ExternalISR31 | ||
| #endif | ||
| .section .vectors, "ax" | ||
| _vectors_end: | ||
|
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| .section .init, "ax" | ||
| .balign 2 | ||
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| .thumb_func | ||
| reset_handler: | ||
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| #ifndef __NO_SYSTEM_INIT | ||
| ldr r0, =__stack_end__ | ||
| mov sp, r0 | ||
| bl SystemInit | ||
| #endif | ||
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| #if !defined(__SOFTFP__) | ||
| // Enable CP11 and CP10 with CPACR |= (0xf<<20) | ||
| movw r0, 0xED88 | ||
| movt r0, 0xE000 | ||
| ldr r1, [r0] | ||
| orrs r1, r1, #(0xf << 20) | ||
| str r1, [r0] | ||
| #endif | ||
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| b _start | ||
|
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| #ifndef __NO_SYSTEM_INIT | ||
| .thumb_func | ||
| .weak SystemInit | ||
| SystemInit: | ||
| bx lr | ||
| #endif |
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