Process-Design-Verilog

A single cycle processor and a pipelined processor in VERILOG.

4-Stage design of processor involves instruction get, instruction decode, ALU, Write-ack stage with pipeline registers

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU.v		ALU.v
EX_WB.v		EX_WB.v
ForwardingMUX.v		ForwardingMUX.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
InstructionMem.v		InstructionMem.v
OutputMUX.v		OutputMUX.v
Processor.v		Processor.v
README.md		README.md
RegisterFile.v		RegisterFile.v

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