Gowin. Add clock wires delays.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
YosysHQ · Aug 20, 2024 · 968da5d · 968da5d
1 parent c064bf1
commit 968da5d
Showing 1 changed file with 12 additions and 4 deletions.
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -362,7 +362,11 @@ def get_wire_type(name):
         for src in srcs.keys():
             if not tt.has_wire(src):
                 tt.create_wire(src, "GLOBAL_CLK")
-            tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
+            src_tm_class = get_tm_class(db, src)
+            if src_tm_class in {'CENT_SPINE_PCLK', 'SPINE_TAP_PCLK', 'TAP_BRANCH_PCLK', 'BRANCH_PCLK'}:
+                tt.create_pip(src, dst, src_tm_class, flags = PIP_FLAG_FIXED_DELAY)
+            else:
+                tt.create_pip(src, dst, src_tm_class)
 
 def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     if (y, x) not in db.hclk_pips:
@@ -1172,7 +1176,7 @@ def group_to_timingvalue(group):
         speed_grades.append(speed)
 
     tmg = chip.set_speed_grades(speed_grades)
-    
+
     print("device {}:".format(chip.name))
     for speed, groups in db.timing.items():
         for group, arc in groups.items():
@@ -1254,7 +1258,11 @@ def group_to_timingvalue(group):
             elif group == "fanout":
                 pass # handled in "wire"
             elif group == "glbsrc":
-                pass # TODO
+                # TODO
+                # no fanout delay for clock wires
+                for name in ["CENT_SPINE_PCLK", "SPINE_TAP_PCLK", "TAP_BRANCH_PCLK"]:
+                    tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]))
+                tmg.set_pip_class(speed, 'GCLK_BRANCH', group_to_timingvalue(arc['BRANCH_PCLK']))
             elif group == "hclk":
                 pass # TODO
             elif group == "iodelay":
@@ -1267,7 +1275,7 @@ def group_to_timingvalue(group):
                 for name in ["X0CTL", "X0CLK", "FX1"]:
                     tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]))
                 # wires with presently-unknown delay
-                for name in ["LUT_IN", "DI", "SEL", "CIN", "COUT", "VCC", "VSS", "LW_TAP", "LW_TAP_0", "LW_BRANCH", "LW_SPAN", "GCLK_TAP", "GCLK_BRANCH"]:
+                for name in ["LUT_IN", "DI", "SEL", "CIN", "COUT", "VCC", "VSS", "LW_TAP", "LW_TAP_0", "LW_BRANCH", "LW_SPAN"]:
                     tmg.set_pip_class(speed, name, TimingValue())
                 # wires with fanout-only delay; used on cell output pips
                 for name, mapping in [("LUT_OUT", "FFan"), ("FF_OUT", "QFan"), ("OF", "OFFan")]: