[arch] support longanpi-4b t527 platform

board/CMakeLists.txt

@@ -16,4 +16,8 @@ endif()
 
 if(CONFIG_BOARD_LONGANPI-3H)
     add_subdirectory(longanpi-3h)
+endif()
+
+if(CONFIG_BOARD_LONGANPI-4B)
+    add_subdirectory(longanpi-4b)
 endif()

board/longanpi-3h/board.c

@@ -77,26 +77,6 @@ void neon_enable(void) {
     asm volatile("MCR p10, 7, r3, c8, c0, 0");
 }
 
-void set_cpu_down(unsigned int cpu) {
-    clrbits_le32(SUNXI_CPUXCFG_BASE + SUNXI_DBG_REG1, 1 << cpu);
-    udelay(10);
-
-    setbits_le32(SUNXI_CPUXCFG_BASE + SUNXI_CLUSTER_PWROFF_GATING, 1 << cpu);
-    udelay(20);
-
-    clrbits_le32(SUNXI_CPUXCFG_BASE + SUNXI_CPU_RST_CTRL, 1 << cpu);
-    udelay(10);
-
-    printk(LOG_LEVEL_DEBUG, "CPU: Power-down cpu-%d ok.\n", cpu);
-}
-
-void set_cpu_poweroff(void) {
-    if (((readl(SUNXI_SID_BASE + 0x248) >> 29) & 0x1) == 1) {
-        set_cpu_down(2); /*power of cpu2*/
-        set_cpu_down(3); /*power of cpu3*/
-    }
-}
-
 void clean_syterkit_data(void) {
     /* Disable MMU, data cache, instruction cache, interrupts */
     arm32_mmu_disable();

board/longanpi-4b/CMakeLists.txt

@@ -2,17 +2,6 @@ set(APP_COMMON_SOURCE
     ${CMAKE_CURRENT_SOURCE_DIR}/start.S 
     ${CMAKE_CURRENT_SOURCE_DIR}/board.c
     ${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c
-    ${CMAKE_CURRENT_SOURCE_DIR}/payloads/init_dram_bin.c
 )
 
 add_subdirectory(hello_world)
-
-add_subdirectory(init_dram)
-
-add_subdirectory(cli_test)
-
-add_subdirectory(arm64_test)
-
-add_subdirectory(smhc_test)
-
-add_subdirectory(syter_boot)

board/longanpi-4b/board.c

@@ -23,8 +23,8 @@
 sunxi_serial_t uart_dbg = {
         .base = SUNXI_UART0_BASE,
         .id = 0,
-        .gpio_tx = {GPIO_PIN(GPIO_PORTH, 0), GPIO_PERIPH_MUX2},
-        .gpio_rx = {GPIO_PIN(GPIO_PORTH, 1), GPIO_PERIPH_MUX2},
+        .gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
+        .gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
 };
 
 sunxi_spi_t sunxi_spi0 = {

board/longanpi-4b/start.S

@@ -43,24 +43,23 @@ reset:
 	msr cpsr_c, r0
 
 	/* Set vector base address register */
-
 	ldr r0, =_vector
 	mcr p15, 0, r0, c12, c0, 0
 	mrc p15, 0, r0, c1, c0, 0
 	bic r0, #(1 << 13)
 	mcr p15, 0, r0, c1, c0, 0
 
-	mrc     p15, 0, r0, c1, c0, 0
-	bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
-	bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
-	orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
-	bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
-	mcr     p15, 0, r0, c1, c0, 0
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #0x00002000     @ clear bits 13 (--V-)
+	bic r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
+	orr r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
+	bic r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
+	mcr p15, 0, r0, c1, c0, 0
 
 	/* Set stack pointer */
 	ldr sp, =__stack_srv_end
 
-	bl  clear_bss
+	bl clear_bss
 
 	/*
 	* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
@@ -74,10 +73,6 @@ reset:
 	orr     r0, r0, #0xc0           @ disable FIQ and IRQ
 	msr     cpsr,r0
 
-	@set cntfrq to 24M
-	ldr r0, =24000000
-	mcr p15, 0, r0, c14, c0, 0
-
 	bl set_timer_count
 
 	bl main

cmake/board/longanpi-4b.cmake

@@ -23,7 +23,7 @@ set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain")
 set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc")
 set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++")
 
-set(CMAKE_COMMON_FLAGS "-nostdlib -Os -mcpu=cortex-a55")
+set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -mcpu=cortex-a55")
 
 # Disable specific warning flags for C and C++ compilers
 set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers")

include/drivers/reg/reg-ncat.h

@@ -13,6 +13,8 @@ extern "C" {
     #include <sun8iw20/reg/reg-ncat.h>
 #elif defined(CONFIG_CHIP_SUN50IW9)
     #include <sun50iw9/reg/reg-ncat.h>
+#elif defined(CONFIG_CHIP_SUN55IW3)
+    #include <sun55iw3/reg/reg-ncat.h>
 #else
     #error "Unsupported chip"
 #endif

include/drivers/sun50iw9/sys-clk.h

@@ -3,10 +3,33 @@
 
 #include "reg/reg-ccu.h"
 
+/**
+ * @brief Initialize the global clocks.
+ *
+ * This function initializes the global clocks, including PLLs and clock dividers.
+ */
 void sunxi_clk_init(void);
 
+/**
+ * @brief Reset the global clocks.
+ *
+ * This function resets all global clocks to their default values.
+ */
 void sunxi_clk_reset(void);
 
+/**
+ * @brief Dump all clock-related register values.
+ *
+ * This function prints out all clock-related register values for debugging and observation.
+ */
 void sunxi_clk_dump(void);
 
+/**
+ * @brief Get the clock rate of the PERI1X bus.
+ *
+ * @return The clock rate of the PERI1X bus in Hz.
+ */
+uint32_t sunxi_clk_get_peri1x_rate();
+
+
 #endif// __SUN50IW9_CLK_H__

include/drivers/sun50iw9/sys-dram.h

@@ -12,6 +12,6 @@
 
 #define SDRAM_BASE (0x40000000)
 
-uint64_t sunxi_dram_init();
+uint64_t sunxi_dram_init(void *para);
 
 #endif // __SUN50IW9_SYS_DRAM_H__

include/drivers/sun55iw3/reg/reg-ccu.h

@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef __SUN55IW3_REG_CCU_H__
+#define __SUN55IW3_REG_CCU_H__
+
+#include <reg-ncat.h>
+
+#include "reg-cpu.h"
+
+#define CCU_BASE SUNXI_CCMU_BASE
+
+#define APB2_CLK_SRC_OSC24M (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define APB2_CLK_SRC_OSC32K (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define APB2_CLK_SRC_PSI (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define APB2_CLK_SRC_PLL6 (APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
+
+#define APB2_CLK_RATE_N_1 (0x0 << 8)
+#define APB2_CLK_RATE_N_2 (0x1 << 8)
+#define APB2_CLK_RATE_N_4 (0x2 << 8)
+#define APB2_CLK_RATE_N_8 (0x3 << 8)
+#define APB2_CLK_RATE_N_MASK (3 << 8)
+#define APB2_CLK_RATE_M(m) (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)
+#define APB2_CLK_RATE_M_MASK (3 << APB1_CLK_REG_FACTOR_M_OFFSET)
+
+/* MMC clock bit field */
+#define CCM_MMC_CTRL_M(x) ((x) -1)
+#define CCM_MMC_CTRL_N(x) ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)
+#define CCM_MMC_CTRL_OSCM24 (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define CCM_MMC_CTRL_PLL6X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define CCM_MMC_CTRL_PLL_PERIPH2X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define CCM_MMC_CTRL_ENABLE (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
+/* if doesn't have these delays */
+#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
+#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)
+
+/* Module gate/reset shift*/
+#define RESET_SHIFT (16)
+#define GATING_SHIFT (0)
+
+/* pll list */
+#define CCU_PLL_CPU0_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000)
+#define CCU_PLL_CPU1_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x04)
+#define CCU_PLL_CPU2_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x08)
+#define CCU_PLL_CPU3_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x0c)
+#define CCU_PLL_DDR0_CTRL_REG (PLL_DDR_CTRL_REG)
+#define CCU_PLL_DDR1_CTRL_REG (0x18)
+#define CCU_PLL_PERI0_CTRL_REG (PLL_PERI0_CTRL_REG)
+#define CCU_PLL_PERI1_CTRL_REG (PLL_PERI1_CTRL_REG)
+#define CCU_PLL_GPU_CTRL_REG (PLL_GPU_CTRL_REG)
+#define CCU_PLL_VIDE00_CTRL_REG (PLL_VIDEO0_CTRL_REG)
+#define CCU_PLL_VIDE01_CTRL_REG (PLL_VIDEO1_CTRL_REG)
+#define CCU_PLL_VIDE02_CTRL_REG (PLL_VIDEO2_CTRL_REG)
+#define CCU_PLL_VIDE03_CTRL_REG (PLL_VIDEO3_CTRL_REG)
+#define CCU_PLL_VE_CTRL_REG (PLL_VE_CTRL_REG)
+#define CCU_PLL_CPUA_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x60)
+#define CCU_PLL_CPUB_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x64)
+#define CCU_PLL_CPU_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x68)
+#define CCU_PLL_DSU_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x6C)
+#define CCU_PLL_AUDIO_CTRL_REG (PLL_AUDIO_CTRL_REG)
+
+
+#define CCU_PLL_HSIC_CTRL_REG (0x70)
+
+
+/* cfg list */
+#define CCU_CPUX_AXI_CFG_REG (CPU_CLK_REG)
+#define CCU_AHB0_CFG_REG (0x510)
+#define CCU_APB0_CFG_REG (0x520)
+#define CCU_APB1_CFG_REG (0x524)
+#define CCU_MBUS_CFG_REG (0x540)
+
+#define CCU_CE_CLK_REG (0x680)
+#define CCU_CE_BGR_REG (0x68C)
+
+#define CCU_VE_CLK_REG (0x690)
+#define CCU_VE_BGR_REG (0x69C)
+
+/*SYS*/
+#define CCU_DMA_BGR_REG (0x70C)
+#define CCU_AVS_CLK_REG (0x750)
+#define CCU_AVS_BGR_REG (0x74C)
+
+/*IOMMU*/
+#define CCU_IOMMU_BGR_REG (0x7bc)
+#define IOMMU_AUTO_GATING_REG (SUNXI_IOMMU_BASE + 0X40)
+
+/* storage */
+#define CCU_DRAM_CLK_REG (0x800)
+#define CCU_MBUS_MAT_CLK_GATING_REG (0x804)
+#define CCU_PLL_DDR_AUX_REG (0x808)
+#define CCU_DRAM_BGR_REG (0x80C)
+
+#define CCU_NAND_CLK_REG (0x810)
+#define CCU_NAND_BGR_REG (0x82C)
+
+#define CCU_SDMMC0_CLK_REG (0x830)
+#define CCU_SDMMC1_CLK_REG (0x834)
+#define CCU_SDMMC2_CLK_REG (0x838)
+#define CCU_SMHC_BGR_REG (0x84c)
+
+/*normal interface*/
+#define CCU_UART_BGR_REG (0x90C)
+#define CCU_TWI_BGR_REG (0x91C)
+#define CCU_SCR_BGR_REG (0x93C)
+#define CCU_SPI0_CLK_REG (0x940)
+#define CCU_SPI1_CLK_REG (0x944)
+#define CCU_SPI_BGR_REG (0x96C)
+#define CCU_USB0_CLK_REG (0xA70)
+#define CCU_USB_BGR_REG (0xA8C)
+
+/*DMA*/
+#define DMA_GATING_BASE CCU_DMA_BGR_REG
+#define DMA_GATING_PASS (1)
+#define DMA_GATING_BIT (0)
+
+/*CE*/
+#define CE_CLK_SRC_MASK (0x7)
+#define CE_CLK_SRC_SEL_BIT (CE_CLK_REG_CLK_SRC_SEL_OFFSET)
+#define CE_CLK_SRC (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)
+
+#define CE_CLK_DIV_RATION_N_BIT (0)
+#define CE_CLK_DIV_RATION_N_MASK (0x0)
+#define CE_CLK_DIV_RATION_N (0)
+
+#define CE_CLK_DIV_RATION_M_BIT (CE_CLK_REG_FACTOR_M_OFFSET)
+#define CE_CLK_DIV_RATION_M_MASK (CE_CLK_REG_FACTOR_M_CLEAR_MASK)
+#define CE_CLK_DIV_RATION_M (0)
+
+#define CE_SCLK_ONOFF_BIT (31)
+#define CE_SCLK_ON (1)
+
+#define CE_GATING_BASE CCU_CE_BGR_REG
+#define CE_GATING_PASS (1)
+#define CE_GATING_BIT (0)
+
+#define CE_RST_REG_BASE CCU_CE_BGR_REG
+
+#define CE_SYS_RST_BIT (CE_BGR_REG_CE_SYS_RST_OFFSET)
+#define CE_RST_BIT (CE_BGR_REG_CE_RST_OFFSET)
+#define CE_DEASSERT (CE_BGR_REG_CE_SYS_RST_DE_ASSERT)
+#define CE_SYS_GATING_BIT (CE_BGR_REG_CE_SYS_GATING_OFFSET)
+
+/*gpadc gate and reset reg*/
+#define CCU_GPADC_BGR_REG (0x09EC)
+/*gpadc gate and reset reg*/
+#define CCU_GPADC_CLK_REG (0x09E0)
+/*lpadc gate and reset reg*/
+#define CCU_LRADC_BGR_REG (0x0A9C)
+
+/* ehci */
+#define BUS_CLK_GATING_REG 0x60
+#define BUS_SOFTWARE_RESET_REG 0x2c0
+#define USBPHY_CONFIG_REG 0xcc
+
+#define USBEHCI0_RST_BIT 24
+#define USBEHCI0_GATIING_BIT 24
+#define USBPHY0_RST_BIT 0
+#define USBPHY0_SCLK_GATING_BIT 8
+
+#define USBEHCI1_RST_BIT 25
+#define USBEHCI1_GATIING_BIT 25
+#define USBPHY1_RST_BIT 1
+#define USBPHY1_SCLK_GATING_BIT 9
+
+/* SPIF clock bit field */
+#define CCM_SPIF_CTRL_M(x) ((x) -1)
+#define CCM_SPIF_CTRL_N(x) ((x) << 8)
+#define CCM_SPIF_CTRL_HOSC (0x0 << 24)
+#define CCM_SPIF_CTRL_PERI400M (0x1 << 24)
+#define CCM_SPIF_CTRL_PERI300M (0x2 << 24)
+#define CCM_SPIF_CTRL_ENABLE (0x1 << 31)
+#define GET_SPIF_CLK_SOURECS(x) (x == CCM_SPIF_CTRL_PERI400M ? 400000000 : 300000000)
+#define CCM_SPIF_CTRL_PERI CCM_SPIF_CTRL_PERI400M
+#define SPIF_RESET_SHIFT (19)
+#define SPIF_GATING_SHIFT (3)
+
+/*E906*/
+#define RISCV_PUBSRAM_CFG_REG (SUNXI_DSP_PRCM_BASE + 0x0114)
+#define RISCV_PUBSRAM_RST (0x1 << 16)
+#define RISCV_PUBSRAM_GATING (0x1 << 0)
+
+#define RISCV_CLK_REG (SUNXI_DSP_PRCM_BASE + 0x0120)
+#define RISCV_CLK_GATING (0x1 << 31)
+
+#define RISCV_CFG_BGR_REG (SUNXI_DSP_PRCM_BASE + 0x0124)
+#define RISCV_CORE_RST (0x1 << 18)
+#define RISCV_APB_DB_RST (0x1 << 17)
+#define RISCV_CFG_RST (0x1 << 16)
+#define RISCV_CFG_GATING (0x1 << 0)
+
+#define RISCV_CFG_BASE (0x07130000)
+#define RISCV_STA_ADD_REG (RISCV_CFG_BASE + 0x0204)
+
+#endif// __SUN55IW3_REG_CCU_H__