[app] add H618 CLK name

YuzukiHD · Dec 27, 2023 · 3addf2a · 3addf2a
1 parent c7325eb
commit 3addf2a
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Showing 3 changed files with 6 additions and 2 deletions.
diff --git a/board/longanpi-3h/init_dram/main.c b/board/longanpi-3h/init_dram/main.c
@@ -26,6 +26,8 @@ int main(void) {
 
     sunxi_dram_init(NULL);
 
+    sunxi_clk_dump();
+
     int i = 0;
 
     while (1) {

diff --git a/src/drivers/sun50iw9/sys-clk.c b/src/drivers/sun50iw9/sys-clk.c
@@ -215,7 +215,7 @@ int sunxi_clock_init_gpadc(void) {
 extern sunxi_serial_t uart_dbg;
 
 void sunxi_clk_init(void) {
-    printk(LOG_LEVEL_DEBUG, "Set SoC AW%04x CLK Start.\n", read32(SUNXI_SID_BASE) & 0xffff);
+    printk(LOG_LEVEL_DEBUG, "Set SoC 1823 (H616/H313/H618) CLK Start.\n");
     set_platform_config();
     set_pll_cpux_axi();
     set_pll_periph0();

diff --git a/src/drivers/sun50iw9/sys-dram.c b/src/drivers/sun50iw9/sys-dram.c
@@ -22,9 +22,11 @@ uint64_t sunxi_dram_init(void *para) {
     uint8_t *src = __ddr_bin_start;
     uint8_t *dst = (uint8_t *) INIT_DRAM_BIN_BASE;
 
-    printk(LOG_LEVEL_DEBUG, "0x%08x -> 0x%08x size: %08x\n", src, dst, __ddr_bin_end - __ddr_bin_start);
+    printk(LOG_LEVEL_DEBUG, "DRAM: load dram init from 0x%08x -> 0x%08x size: %08x\n", src, dst, __ddr_bin_end - __ddr_bin_start);
     memcpy(dst, src, __ddr_bin_end - __ddr_bin_start);
 
+    printk(LOG_LEVEL_DEBUG, "DRAM: Now jump to 0x%08x run DRAMINIT\n",dst);
+
     __asm__ __volatile__("isb sy"
                          :
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