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[driver] support longanpi-4b smhc
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@YuzukiTsuru
YuzukiTsuru committed Jan 4, 2024
1 parent 9d4fa4f commit 42d72ca
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Showing 5 changed files with 101 additions and 62 deletions.
116 changes: 71 additions & 45 deletions include/drivers/sun55iw3/reg/reg-smhc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -188,50 +188,76 @@ timing mode
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)

typedef struct {
volatile uint32_t gctrl; /* (0x00) SMC Global Control Register */
volatile uint32_t clkcr; /* (0x04) SMC Clock Control Register */
volatile uint32_t timeout; /* (0x08) SMC Time Out Register */
volatile uint32_t width; /* (0x0C) SMC Bus Width Register */
volatile uint32_t blksz; /* (0x10) SMC Block Size Register */
volatile uint32_t bytecnt; /* (0x14) SMC Byte Count Register */
volatile uint32_t cmd; /* (0x18) SMC Command Register */
volatile uint32_t arg; /* (0x1C) SMC Argument Register */
volatile uint32_t resp0; /* (0x20) SMC Response Register 0 */
volatile uint32_t resp1; /* (0x24) SMC Response Register 1 */
volatile uint32_t resp2; /* (0x28) SMC Response Register 2 */
volatile uint32_t resp3; /* (0x2C) SMC Response Register 3 */
volatile uint32_t imask; /* (0x30) SMC Interrupt Mask Register */
volatile uint32_t mint; /* (0x34) SMC Masked Interrupt Status Register */
volatile uint32_t rint; /* (0x38) SMC Raw Interrupt Status Register */
volatile uint32_t status; /* (0x3C) SMC Status Register */
volatile uint32_t ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Register */
volatile uint32_t funcsel; /* (0x44) SMC Function Select Register */
volatile uint32_t cbcr; /* (0x48) SMC CIU Byte Count Register */
volatile uint32_t bbcr; /* (0x4C) SMC BIU Byte Count Register */
volatile uint32_t dbgc; /* (0x50) SMC Debug Enable Register */
volatile uint32_t csdc; /* (0x54) CRC status detect control register*/
volatile uint32_t a12a; /* (0x58)Auto command 12 argument*/
volatile uint32_t ntsr; /* (0x5c)SMC2 Newtiming Set Register */
volatile uint32_t res1[6]; /* (0x54~0x74) */
volatile uint32_t hwrst; /* (0x78) SMC eMMC Hardware Reset Register */
volatile uint32_t res2; /* (0x7c) */
volatile uint32_t dmac; /* (0x80) SMC IDMAC Control Register */
volatile uint32_t dlba; /* (0x84) SMC IDMAC Descriptor List Base Address Register */
volatile uint32_t idst; /* (0x88) SMC IDMAC Status Register */
volatile uint32_t idie; /* (0x8C) SMC IDMAC Interrupt Enable Register */
volatile uint32_t chda; /* (0x90) */
volatile uint32_t cbda; /* (0x94) */
volatile uint32_t res3[26]; /* (0x98~0xff) */
volatile uint32_t thldc; /* (0x100) Card Threshold Control Register */
volatile uint32_t sfc; /* 0x104 SMC Sample FIFO Control Register */
volatile uint32_t res4[1]; /* 0x108 */
volatile uint32_t dsbd; /* (0x10c) eMMC4.5 DDR Start Bit Detection Control */
volatile uint32_t res5[12]; /* (0x110~0x13c) */
volatile uint32_t drv_dl; /* (0x140) drive delay control register*/
volatile uint32_t samp_dl; /* (0x144) sample delay control register*/
volatile uint32_t ds_dl; /* (0x148) data strobe delay control register */
volatile uint32_t res6[45]; /* (0x110~0x1ff) */
volatile uint32_t fifo; /* (0x200) SMC FIFO Access Address */
volatile uint32_t gctrl; /* (0x00) SMC Global Control Register */
volatile uint32_t clkcr; /* (0x04) SMC Clock Control Register */
volatile uint32_t timeout; /* (0x08) SMC Time Out Register */
volatile uint32_t width; /* (0x0C) SMC Bus Width Register */
volatile uint32_t blksz; /* (0x10) SMC Block Size Register */
volatile uint32_t bytecnt; /* (0x14) SMC Byte Count Register */
volatile uint32_t cmd; /* (0x18) SMC Command Register */
volatile uint32_t arg; /* (0x1C) SMC Argument Register */
volatile uint32_t resp0; /* (0x20) SMC Response Register 0 */
volatile uint32_t resp1; /* (0x24) SMC Response Register 1 */
volatile uint32_t resp2; /* (0x28) SMC Response Register 2 */
volatile uint32_t resp3; /* (0x2C) SMC Response Register 3 */
volatile uint32_t imask; /* (0x30) SMC Interrupt Mask Register */
volatile uint32_t mint; /* (0x34) SMC Masked Interrupt Status Register */
volatile uint32_t rint; /* (0x38) SMC Raw Interrupt Status Register */
volatile uint32_t status; /* (0x3C) SMC Status Register */
volatile uint32_t
ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Register */
volatile uint32_t funcsel; /* (0x44) SMC Function Select Register */
volatile uint32_t cbcr; /* (0x48) SMC CIU Byte Count Register */
volatile uint32_t bbcr; /* (0x4C) SMC BIU Byte Count Register */
volatile uint32_t dbgc; /* (0x50) SMC Debug Enable Register */
volatile uint32_t csdc; /* (0x54) CRC status detect control register*/
volatile uint32_t a12a; /* (0x58)Auto command 12 argument*/
volatile uint32_t ntsr; /* (0x5c)SMC2 Newtiming Set Register */
volatile uint32_t res1[6]; /* (0x60~0x74) */
volatile uint32_t hwrst; /* (0x78) SMC eMMC Hardware Reset Register */
volatile uint32_t res2; /* (0x7c) */
volatile uint32_t dmac; /* (0x80) SMC IDMAC Control Register */
volatile uint32_t
dlba; /* (0x84) SMC IDMAC Descriptor List Base Address Register */
volatile uint32_t idst; /* (0x88) SMC IDMAC Status Register */
volatile uint32_t idie; /* (0x8C) SMC IDMAC Interrupt Enable Register */
volatile uint32_t chda; /* (0x90) */
volatile uint32_t cbda; /* (0x94) */
volatile uint32_t res3[26]; /* (0x98~0xff) */
volatile uint32_t thldc; /* (0x100) Card Threshold Control Register */
volatile uint32_t sfc; /* (0x104) Sample Fifo Control Register */
volatile uint32_t res4[1]; /* (0x10b) */
volatile uint32_t
dsbd; /* (0x10c) eMMC4.5 DDR Start Bit Detection Control */
volatile uint32_t res5[12]; /* (0x110~0x13c) */
volatile uint32_t drv_dl; /* (0x140) Drive Delay Control register*/
volatile uint32_t samp_dl; /* (0x144) Sample Delay Control register*/
volatile uint32_t ds_dl; /* (0x148) Data Strobe Delay Control Register */
volatile uint32_t
ntdc; /* (0x14C) HS400 New Timing Delay Control Register */
volatile uint32_t res6[4]; /* (0x150~0x15f) */
volatile uint32_t
skew_dat0_dl; /*(0x160) deskew data0 delay control register*/
volatile uint32_t
skew_dat1_dl; /*(0x164) deskew data1 delay control register*/
volatile uint32_t
skew_dat2_dl; /*(0x168) deskew data2 delay control register*/
volatile uint32_t
skew_dat3_dl; /*(0x16c) deskew data3 delay control register*/
volatile uint32_t
skew_dat4_dl; /*(0x170) deskew data4 delay control register*/
volatile uint32_t
skew_dat5_dl; /*(0x174) deskew data5 delay control register*/
volatile uint32_t
skew_dat6_dl; /*(0x178) deskew data6 delay control register*/
volatile uint32_t
skew_dat7_dl; /*(0x17c) deskew data7 delay control register*/
volatile uint32_t skew_ds_dl; /*(0x180) deskew ds delay control register*/
volatile uint32_t skew_ctrl; /*(0x184) deskew control control register*/
volatile uint32_t res8[30]; /* (0x188~0x1ff) */
volatile uint32_t fifo; /* (0x200) SMC FIFO Access Address */
volatile uint32_t res7[63]; /* (0x201~0x2FF)*/
volatile uint32_t vers; /* (0x300) SMHC Version Register */
} sdhci_reg_t;

#endif// __REG_SMHC_H__
#endif // __REG_SMHC_H__
2 changes: 1 addition & 1 deletion payloads
Submodule payloads updated from 2441a0 to 6d8024
2 changes: 1 addition & 1 deletion src/drivers/sun55iw3/sys-clk.c
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Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,7 @@ uint32_t sunxi_clk_get_peri1x_rate() {
uint8_t plln, pllm, p0;

/* PLL PERI */
reg32 = read32(CCU_BASE + CCU_BASE + CCU_BASE + CCU_PLL_PERI0_CTRL_REG);
reg32 = read32(CCU_BASE + CCU_PLL_PERI0_CTRL_REG);
if (reg32 & (1 << 31)) {
plln = ((reg32 >> 8) & 0xff) + 1;
pllm = (reg32 & 0x01) + 1;
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/sun55iw3/sys-dram.c
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
#include <sys-dram.h>
#include <sys-rtc.h>

#define INIT_DRAM_BIN_BASE 0x38000
#define INIT_DRAM_BIN_BASE 0x4c000

extern uint8_t __ddr_bin_start[];
extern uint8_t __ddr_bin_end[];
Expand Down
41 changes: 27 additions & 14 deletions src/drivers/sun55iw3/sys-sdhci.c
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,6 @@

#define FALSE 0
#define TRUE 1

static void set_read_timeout(sdhci_t *sdhci, uint32_t timeout) {
uint32_t rval = 0;
uint32_t rdto_clk = 0;
Expand Down Expand Up @@ -433,6 +432,23 @@ bool sdhci_set_width(sdhci_t *sdhci, uint32_t width) {
return TRUE;
}

static int init_default_timing(sdhci_t *sdhci) {
printk(LOG_LEVEL_TRACE, "SMHC: init_default_timing start\n");

sdhci->odly[MMC_CLK_400K] = TM5_OUT_PH180;
sdhci->odly[MMC_CLK_25M] = TM5_OUT_PH180;
sdhci->odly[MMC_CLK_50M] = TM5_OUT_PH180;
sdhci->odly[MMC_CLK_50M_DDR] = TM5_OUT_PH90;

sdhci->sdly[MMC_CLK_400K] = TM5_IN_PH180;
sdhci->sdly[MMC_CLK_25M] = TM5_IN_PH180;
sdhci->sdly[MMC_CLK_50M] = TM5_IN_PH90;
sdhci->sdly[MMC_CLK_50M_DDR] = TM5_IN_PH180;

printk(LOG_LEVEL_TRACE, "SMHC: init_default_timing done\n");
return 0;
}

static int config_delay(sdhci_t *sdhci) {
uint32_t rval, freq, val;
uint8_t odly, sdly;
Expand Down Expand Up @@ -460,6 +476,11 @@ static int config_delay(sdhci_t *sdhci) {
rval |= ((sdly & 0x3) << 8);
sdhci->reg->ntsr = rval;

/*enable hw skew auto mode*/
rval = sdhci->reg->skew_ctrl;
rval |= (0x1 << 4);
sdhci->reg->skew_ctrl = rval;

return 0;
}

Expand Down Expand Up @@ -586,19 +607,6 @@ bool sdhci_set_clock(sdhci_t *sdhci, smhc_clk_t clock) {
return true;
}

static int init_default_timing(sdhci_t *sdhci) {
sdhci->odly[MMC_CLK_400K] = TM5_OUT_PH180;
sdhci->odly[MMC_CLK_25M] = TM5_OUT_PH180;
sdhci->odly[MMC_CLK_50M] = TM5_OUT_PH180;
sdhci->odly[MMC_CLK_50M_DDR] = TM5_OUT_PH90;

sdhci->sdly[MMC_CLK_400K] = TM5_IN_PH180;
sdhci->sdly[MMC_CLK_25M] = TM5_IN_PH180;
sdhci->sdly[MMC_CLK_50M] = TM5_IN_PH90;
sdhci->sdly[MMC_CLK_50M_DDR] = TM5_IN_PH180;
return 0;
}

int sunxi_sdhci_init(sdhci_t *sdhci) {
sunxi_gpio_init(sdhci->gpio_clk.pin, sdhci->gpio_clk.mux);
sunxi_gpio_set_pull(sdhci->gpio_clk.pin, GPIO_PULL_UP);
Expand All @@ -621,6 +629,11 @@ int sunxi_sdhci_init(sdhci_t *sdhci) {
init_default_timing(sdhci);
sdhci_set_clock(sdhci, MMC_CLK_400K);

sdhci->reg->gctrl = SMHC_GCTRL_HARDWARE_RESET;
sdhci->reg->rint = 0xffffffff;

sdhci->dma_trglvl = ((0x3 << 28) | (15 << 16) | 240);

udelay(100);

return 0;
Expand Down

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