[app] add init dram

app/CMakeLists.txt

@@ -2,5 +2,6 @@
 
 add_subdirectory(hello_world)
 add_subdirectory(read_chipsid)
+add_subdirectory(init_dram)
 add_subdirectory(read_chip_efuse)
 add_subdirectory(syter_boot)

app/init_dram/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_syterkit_app(initdram 
+    start.S 
+    main.c
+)

app/init_dram/main.c

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <types.h>
+
+#include <log.h>
+
+#include <common.h>
+
+#include <config.h>
+
+extern uint32_t _start;
+extern uint32_t __spl_start;
+extern uint32_t __spl_end;
+extern uint32_t __spl_size;
+extern uint32_t __stack_srv_start;
+extern uint32_t __stack_srv_end;
+extern uint32_t __stack_ddr_srv_start;
+extern uint32_t __stack_ddr_srv_end;
+
+sunxi_uart_t uart_dbg = {
+	.base = 0x02500000,
+	.id = 0,
+	.gpio_tx = { GPIO_PIN(PORTH, 9), GPIO_PERIPH_MUX5 },
+	.gpio_rx = { GPIO_PIN(PORTH, 10), GPIO_PERIPH_MUX5 },
+};
+
+void show_banner(void)
+{
+	uint32_t id[4];
+
+	printk(LOG_LEVEL_MUTE, "\r\n");
+	printk(LOG_LEVEL_INFO, " _____     _           _____ _ _   \r\n");
+	printk(LOG_LEVEL_INFO, "|   __|_ _| |_ ___ ___|  |  |_| |_ \r\n");
+	printk(LOG_LEVEL_INFO, "|__   | | |  _| -_|  _|    -| | _| \r\n");
+	printk(LOG_LEVEL_INFO, "|_____|_  |_| |___|_| |__|__|_|_|  \r\n");
+	printk(LOG_LEVEL_INFO, "      |___|                        \r\n");
+	printk(LOG_LEVEL_INFO, "***********************************\r\n");
+	printk(LOG_LEVEL_INFO, " %s V0.1.1 Commit: %s\r\n", PROJECT_NAME,
+	       PROJECT_GIT_HASH);
+	printk(LOG_LEVEL_INFO, "***********************************\r\n");
+
+	id[0] = read32(0x03006200 + 0x0);
+	id[1] = read32(0x03006200 + 0x4);
+	id[2] = read32(0x03006200 + 0x8);
+	id[3] = read32(0x03006200 + 0xc);
+
+	printk(LOG_LEVEL_INFO, "Chip ID is: %08x%08x%08x%08x\r\n", id[0], id[1],
+	       id[2], id[3]);
+}
+
+void abort(void)
+{
+	while (1)
+		;
+}
+
+int main(void)
+{
+	sunxi_uart_init(&uart_dbg);
+
+	show_banner();
+
+	sunxi_clk_init();
+
+	sunxi_dram_init();
+
+	return 0;
+}

app/init_dram/start.S

@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <linkage.h>
+
+#define  ARMV7_USR_MODE        0x10
+#define  ARMV7_FIQ_MODE        0x11
+#define  ARMV7_IRQ_MODE        0x12
+#define  ARMV7_SVC_MODE        0x13
+#define  ARMV7_MON_MODE        0x16
+#define  ARMV7_ABT_MODE        0x17
+#define  ARMV7_UND_MODE        0x1b
+#define  ARMV7_SYSTEM_MODE     0x1f
+#define  ARMV7_MODE_MASK       0x1f
+#define  ARMV7_FIQ_MASK        0x40
+#define  ARMV7_IRQ_MASK        0x80
+
+.arm
+.globl reset
+.text
+
+reset:
+	/* Boot head information for BROM */
+	.long 0xea000016
+	.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
+	.long 0x12345678                                /* checksum */
+	.long __spl_size                                /* spl size */
+	.long 0x30                                              /* boot header size */
+	.long 0x30303033                                /* boot header version */
+	.long 0x00020000                                /* return value */
+	.long 0x00028000                                /* run address */
+	.long 0x0                                               /* eGON version */
+	.byte 0x00, 0x00, 0x00, 0x00    /* platform information - 8byte */
+	.byte 0x34, 0x2e, 0x30, 0x00
+
+/*
+ * The actual reset code
+ */
+	mrs r0, cpsr
+	bic r0, r0, #ARMV7_MODE_MASK
+	orr r0, r0, #ARMV7_SVC_MODE
+	orr r0, r0, #(ARMV7_IRQ_MASK | ARMV7_FIQ_MASK)
+	bic r0, r0, #(1<<9)     @set little-endian
+	msr cpsr_c, r0
+
+/* Set vector base address register */
+
+	ldr r0, =_vector
+	mcr p15, 0, r0, c12, c0, 0
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, #(1 << 13)
+	mcr p15, 0, r0, c1, c0, 0
+
+	mrc     p15, 0, r0, c1, c0, 0
+	bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
+	bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
+	orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
+	bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
+	mcr     p15, 0, r0, c1, c0, 0
+
+	/* Enable neon/vfp unit */
+	mrc p15, 0, r0, c1, c0, 2
+	orr r0, r0, #(0xf << 20)
+	mcr p15, 0, r0, c1, c0, 2
+	isb
+	mov r0, #0x40000000
+	vmsr fpexc, r0
+
+	/* Set stack pointer */
+	ldr sp, =__stack_srv_end
+
+	bl  clear_bss
+
+	/*
+		* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
+		* except if in HYP mode already
+		*/
+	mrs     r0, cpsr
+	and     r1, r0, #0x1f           @ mask mode bits
+	teq     r1, #0x1a               @ test for HYP mode
+	bicne   r0, r0, #0x1f           @ clear all mode bits
+	orrne   r0, r0, #0x13           @ set SVC mode
+	orr     r0, r0, #0xc0           @ disable FIQ and IRQ
+	msr     cpsr,r0
+
+	@set cntfrq to 24M
+	ldr r0, =24000000
+	mcr p15, 0, r0, c14, c0, 0
+
+	bl set_timer_count
+
+	bl main
+
+	clear_bss:
+	ldr     r0, =_sbss
+	ldr     r1, =_ebss
+	mov     r2, #0
+
+	clbss_1:
+	stmia   r0!, {r2}
+	cmp r0, r1
+	blt clbss_1
+
+	mov pc, lr
+
+_vector:
+	b reset
+	ldr pc, _undefined_instruction
+	ldr pc, _software_interrupt
+	ldr pc, _prefetch_abort
+	ldr pc, _data_abort
+	ldr pc, _not_used
+	ldr pc, _irq
+	ldr pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+
+.macro save_regs
+	str lr, [sp, #-4]
+	mrs lr, spsr_all
+	str lr, [sp, #-8]
+	str r1, [sp, #-12]
+	str r0, [sp, #-16]
+	mov r0, sp
+	cps #0x13
+	ldr r1, [r0, #-4]
+	str r1, [sp, #-4]!
+	ldr r1, [r0, #-8]
+	str r1, [sp, #-(4 * 16)]
+	ldr r1, [r0, #-12]
+	ldr r0, [r0, #-16]
+	stmdb sp, {r0 - r14}^
+	sub sp, sp, #(4 * 16)
+	ldr r4, [sp]
+	and r0, r4, #0x1f
+	cmp r0, #0x10
+	beq 10f
+	cmp r0, #0x13
+	beq 11f
+	b .
+11:	add r1, sp, #(4 * 17)
+	str r1, [sp, #(4 * 14)]
+	str lr, [sp, #(4 * 15)]
+10:	add r1, sp, #(4 * 17)
+	str r1, [sp, #-4]!
+	mov r0, sp
+.endm
+
+.macro restore_regs
+	mov r12, sp
+	ldr sp, [r12], #4
+	ldr r1, [r12], #4
+	msr spsr_cxsf, r1
+	and r0, r1, #0x1f
+	cmp r0, #0x10
+	beq 20f
+	cmp r0, #0x13
+	beq 21f
+	b .
+20:	ldr lr, [r12, #(4 * 15)]
+	ldmia r12, {r0 - r14}^
+	movs pc, lr
+21:	ldm r12, {r0 - r15}^
+	mov r0, r0
+.endm
+
+/*
+ * Exception handlers
+ */
+	.align 5
+undefined_instruction:
+	sub lr, lr, #4
+	save_regs
+	bl arm32_do_undefined_instruction
+	restore_regs
+
+	.align 5
+software_interrupt:
+	sub lr, lr, #4
+	save_regs
+	bl arm32_do_software_interrupt
+	restore_regs
+
+	.align 5
+prefetch_abort:
+	sub lr, lr, #4
+	save_regs
+	bl arm32_do_prefetch_abort
+	restore_regs
+
+	.align 5
+data_abort:
+	sub lr, lr, #8
+	save_regs
+	bl arm32_do_data_abort
+	restore_regs
+
+	.align 5
+not_used:
+	b .
+
+	.align 5
+irq:
+	sub lr, lr, #4
+	save_regs
+	bl arm32_do_irq
+	restore_regs
+
+	.align 5
+fiq:
+	sub lr, lr, #4
+	save_regs
+	bl arm32_do_fiq
+	restore_regs