[arch] add board longanpi-3h

.gitignore

@@ -3,3 +3,4 @@ test/
 tools/*.bin
 mksunxi
 .vscode/settings.json
+prebuilt/

board/CMakeLists.txt

@@ -12,4 +12,8 @@ endif()
 
 if(CONFIG_BOARD_100ASK-T113I)
     add_subdirectory(100ask-t113i)
+endif()
+
+if(CONFIG_BOARD_LONGANPI-3H)
+    add_subdirectory(longanpi-3h)
 endif()

board/longanpi-3h/CMakeLists.txt

@@ -0,0 +1,7 @@
+set(APP_COMMON_SOURCE 
+    ${CMAKE_CURRENT_SOURCE_DIR}/start.S 
+    ${CMAKE_CURRENT_SOURCE_DIR}/board.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c
+)
+
+add_subdirectory(hello_world)

board/longanpi-3h/README.md

@@ -0,0 +1,29 @@
+# SyterKit Common 
+
+## start.S
+
+This code snippet is an ARM assembly language program that includes initialization settings and exception handlers. Here's a breakdown of its functionalities:
+
+1. Initialization Settings: It sets registers and writes specific values to configure the processor's working mode, interrupt enable, etc.
+
+2. Set Vector Table: It writes the address of the vector table to the Vector Base Address Register, which is used for handling exceptions and interrupts.
+
+3. Enable NEON/VFP Unit: It configures the processor to enable the NEON (Advanced SIMD) and VFP (Floating-Point) units.
+
+4. Clear BSS Section: It zeroes out variables in the BSS section.
+
+5. Disable Interrupts: It disables FIQ and IRQ interrupts and switches the processor to SVC32 mode.
+
+6. Set Timer Frequency: It sets the timer frequency to 24M.
+
+7. Call the main Function: It jumps to the main function to execute the main logic.
+
+## eabi_compat.c
+
+This code snippet appears to be providing implementations for the functions `abort`, `raise`, and `__aeabi_unwind_cpp_pr0`. Here's a breakdown of their functionalities:
+
+1. `void abort(void)`: This function creates an infinite loop, causing the program to hang indefinitely. It is typically used to indicate a critical error or unrecoverable condition in a program.
+
+2. `int raise(int signum)`: This function is a placeholder and always returns 0. In standard C, this function is used to raise a signal and initiate the corresponding signal handler. However, in this implementation, it does nothing and simply returns 0.
+
+3. `void __aeabi_unwind_cpp_pr0(void)`: This is a dummy function that serves as a placeholder to avoid linker complaints. Its purpose is to satisfy the linker when using C++ exceptions and unwinding, but it does not contain any actual functionality.

board/longanpi-3h/board.c

@@ -0,0 +1,93 @@
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <types.h>
+
+#include <log.h>
+
+#include <common.h>
+
+#include <sys-clk.h>
+#include <reg-ncat.h>
+
+#include <mmu.h>
+
+#include <sys-gpio.h>
+#include <sys-spi.h>
+#include <sys-uart.h>
+#include <sys-dram.h>
+#include <sys-sdcard.h>
+
+sunxi_serial_t uart_dbg = {
+        .base = SUNXI_UART0_BASE,
+        .id = 0,
+        .gpio_tx = {GPIO_PIN(GPIO_PORTH, 0), GPIO_PERIPH_MUX2},
+        .gpio_rx = {GPIO_PIN(GPIO_PORTH, 1), GPIO_PERIPH_MUX2},
+};
+
+sunxi_spi_t sunxi_spi0 = {
+        .base = SUNXI_SPI0_BASE,
+        .id = 0,
+        .clk_rate = 75 * 1000 * 1000,
+        .gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
+        .gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
+        .gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
+        .gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
+        .gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
+        .gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
+};
+
+sdhci_t sdhci0 = {
+        .name = "sdhci0",
+        .reg = (sdhci_reg_t *) SUNXI_SMHC0_BASE,
+        .voltage = MMC_VDD_27_36,
+        .width = MMC_BUS_WIDTH_4,
+        .clock = MMC_CLK_50M,
+        .removable = 0,
+        .isspi = FALSE,
+        .gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2},
+        .gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2},
+        .gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2},
+        .gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2},
+        .gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2},
+        .gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2},
+};
+
+dram_para_t dram_para = {
+        .dram_clk = 792,
+        .dram_type = 3,
+        .dram_zq = 0x7b7bfb,
+        .dram_odt_en = 0x00,
+        .dram_para1 = 0x000010d2,
+        .dram_para2 = 0,
+        .dram_mr0 = 0x1c70,
+        .dram_mr1 = 0x42,
+        .dram_mr2 = 0x18,
+        .dram_mr3 = 0,
+        .dram_tpr0 = 0x004a2195,
+        .dram_tpr1 = 0x02423190,
+        .dram_tpr2 = 0x0008b061,
+        .dram_tpr3 = 0xb4787896,// unused
+        .dram_tpr4 = 0,
+        .dram_tpr5 = 0x48484848,
+        .dram_tpr6 = 0x00000048,
+        .dram_tpr7 = 0x1620121e,// unused
+        .dram_tpr8 = 0,
+        .dram_tpr9 = 0,// clock?
+        .dram_tpr10 = 0,
+        .dram_tpr11 = 0x00340000,
+        .dram_tpr12 = 0x00000046,
+        .dram_tpr13 = 0x34000100,
+};
+
+void clean_syterkit_data(void) {
+    /* Disable MMU, data cache, instruction cache, interrupts */
+    arm32_mmu_disable();
+    printk(LOG_LEVEL_INFO, "disable mmu ok...\n");
+    arm32_dcache_disable();
+    printk(LOG_LEVEL_INFO, "disable dcache ok...\n");
+    arm32_icache_disable();
+    printk(LOG_LEVEL_INFO, "disable icache ok...\n");
+    arm32_interrupt_disable();
+    printk(LOG_LEVEL_INFO, "free interrupt ok...\n");
+}

board/longanpi-3h/eabi_compat.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+void abort(void) {
+    while (1)
+        ;
+}
+
+int raise(int signum) {
+    return 0;
+}
+
+/* Dummy function to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void) {
+}

board/longanpi-3h/hello_world/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_syterkit_app(helloworld 
+    main.c
+)

board/longanpi-3h/hello_world/main.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <types.h>
+
+#include <log.h>
+
+#include <sys-dram.h>
+
+extern sunxi_serial_t uart_dbg;
+
+int main(void) {
+    sunxi_serial_init(&uart_dbg);
+
+    //sunxi_clk_init();
+
+    //sunxi_clk_dump();
+
+    while (1) {
+        sunxi_serial_putc(&uart_dbg, 'H');
+    }
+
+    return 0;
+}

board/longanpi-3h/start.S

@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+#include <linkage.h>
+
+#define  ARMV7_USR_MODE           0x10
+#define  ARMV7_FIQ_MODE           0x11
+#define  ARMV7_IRQ_MODE           0x12
+#define  ARMV7_SVC_MODE           0x13
+#define  ARMV7_MON_MODE        	  0x16
+#define  ARMV7_ABT_MODE           0x17
+#define  ARMV7_UND_MODE           0x1b
+#define  ARMV7_SYSTEM_MODE        0x1f
+#define  ARMV7_MODE_MASK          0x1f
+#define  ARMV7_FIQ_MASK           0x40
+#define  ARMV7_IRQ_MASK           0x80
+
+.arm
+.globl reset
+.text
+
+reset:
+	/* Boot head information for BROM */
+	.long 0xea000016
+	.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
+	.long 0x12345678                                /* checksum */
+	.long __spl_size                                /* spl size */
+	.long 0x30                                      /* boot header size */
+	.long 0x30303033                                /* boot header version */
+	.long 0x00020000                                /* return value */
+	.long 0x00028000                                /* run address */
+	.long 0x0                                       /* eGON version */
+	.byte 0x00, 0x00, 0x00, 0x00    				/* platform information - 8byte */
+	.byte 0x34, 0x2e, 0x30, 0x00
+
+	mrs r0, cpsr
+	bic r0, r0, #ARMV7_MODE_MASK
+	orr r0, r0, #ARMV7_SVC_MODE
+	orr r0, r0, #(ARMV7_IRQ_MASK | ARMV7_FIQ_MASK)
+	bic r0, r0, #(1<<9)     @set little-endian
+	msr cpsr_c, r0
+
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
+	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
+	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
+	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/* Set stack pointer */
+	ldr sp, =__stack_srv_end
+
+	bl  clear_bss
+	bl  main
+
+clear_bss:
+	ldr     r0, =_sbss
+	ldr     r1, =_ebss
+	mov     r2, #0
+
+clbss_1:
+	stmia   r0!, {r2}
+	cmp r0, r1
+	blt clbss_1
+
+	mov pc, lr
+

cmake/board/longanpi-3h.cmake

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(CONFIG_ARCH_ARM32 True)
+set(CONFIG_ARCH_ARM32_ARM64 True)
+set(CONFIG_CHIP_SUN50IW9 True)
+set(CONFIG_BOARD_LONGANPI-3H True)
+
+add_definitions(-DCONFIG_CHIP_SUN50IW9)
+
+# Options
+
+# By setting ENABLE_HARDFP to ON, it indicates that the project is configured
+# to utilize hard floating-point operations when applicable. This can be beneficial 
+# in scenarios where performance gains from hardware acceleration are desired.
+set(ENABLE_HARDFP OFF)
+
+# Set the cross-compile toolchain
+set(CROSS_COMPILE "arm-none-eabi-")
+set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain")
+
+# Set the C and C++ compilers
+set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc")
+set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++")
+
+# Configure compiler flags based on ENABLE_HARDFP option
+if(ENABLE_HARDFP)
+    set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53 -mthumb-interwork -mthumb -mno-unaligned-access -mfpu=neon-vfpv4 -mfloat-abi=hard")
+else()
+    set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53 -mthumb-interwork -mthumb -mno-unaligned-access -mfpu=neon-vfpv4 -mfloat-abi=softfp")
+endif()
+
+# Disable specific warning flags for C and C++ compilers
+set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers")
+set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast")
+
+set(ARCH_BIN_START_ADDRESS "0x00020000")
+set(ARCH_BIN_SRAM_LENGTH "128K")
+
+set(ARCH_FEL_START_ADDRESS "0x00028000")
+set(ARCH_FEL_SRAM_LENGTH "100K")