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[rust] upgrade to latest allwinner-hal smhc peripherals
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Signed-off-by: Zhouqi Jiang <luojia@hust.edu.cn>
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luojia65 committed Oct 12, 2024
1 parent f595b34 commit 9ebfbd4
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Showing 3 changed files with 31 additions and 14 deletions.
6 changes: 3 additions & 3 deletions Cargo.lock

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11 changes: 9 additions & 2 deletions board/100ask-d1-h-rs/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,16 @@ fn main(p: Peripherals, _c: Clocks) {
let d2 = p.gpio.pf5.into_function::<2>();
(clk, cmd, d0, d1, d2, d3)
};
unsafe {
p.ccu
.smhc_bgr
.modify(|val| val.gate_pass::<0>().deassert_reset::<0>());
// p.ccu.smhc_clk[0].modify(|val| val.unmask_clock());
p.smhc0
.global_control
.modify(|val| val.set_dma_reset().set_fifo_reset().set_software_reset());
};
/*
p.ccu.smhc_bgr.modify(|val| val.gate_pass::<0>().deassert_reset::<0>()); // 0 == sdhci->id
p.ccu.smhc0_clk.modify(|val| val.unmask_clock());
// let sdhci = p.smhc0.smhc(sdmmc_pins)
// sdhci.detect_sdcard() // TODO or: detect_mmc()
p.smhc0.global_control.modify(|val| val.set_dma_reset().set_fifo_reset().set_software_reset());
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28 changes: 19 additions & 9 deletions rust/src/soc/sun20iw1.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,22 +3,29 @@ use allwinner_hal::{
ccu::{Clocks, CpuClockSource},
gpio::{Disabled, Function},
};
use allwinner_rt::soc::d1::{CCU, COM, GPIO, PHY, PLIC, SPI0, UART0};
use allwinner_rt::soc::d1::{CCU, COM, GPIO, PHY, PLIC, SMHC0, SMHC1, SMHC2, SPI0, UART0};
use embedded_time::rate::Extensions;

/// SyterKit runtime peripheral ownership and configurations.
pub struct Peripherals<'a> {
/// General Purpose Input/Output peripheral.
pub gpio: Pads<'a>,
/// Clock control unit peripheral.
pub ccu: CCU,
// uart0 is removed; it is occupied by stdin/stdout `Serial` structure.
/// Serial Peripheral Interface peripheral 0.
pub spi0: SPI0,
/// Memory controller physical layer (PHY) of DDR SDRAM.
pub phy: PHY,
/// Common control peripheral of DDR SDRAM.
pub com: COM,
/// Clock control unit peripheral.
pub ccu: CCU,
/// Memory controller physical layer (PHY) of DDR SDRAM.
pub phy: PHY,
/// SD/MMC Host Controller peripheral 0.
pub smhc0: SMHC0,
/// SD/MMC Host Controller peripheral 1.
pub smhc1: SMHC1,
/// SD/MMC Host Controller peripheral 2.
pub smhc2: SMHC2,
/// Serial Peripheral Interface peripheral 0.
pub spi0: SPI0,
/// Platform-local Interrupt Controller.
pub plic: PLIC,
}
Expand All @@ -39,10 +46,13 @@ impl<'a> Peripherals<'a> {
let uart0 = src.uart0;
let p = Self {
gpio: Pads::__init(),
spi0: src.spi0,
phy: src.phy,
com: src.com,
ccu: src.ccu,
com: src.com,
phy: src.phy,
smhc0: src.smhc0,
smhc1: src.smhc1,
smhc2: src.smhc2,
spi0: src.spi0,
plic: src.plic,
};
(p, uart0, pb8, pb9)
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