[arch] add baisc riscv64 function

CMakeLists.txt

@@ -103,22 +103,42 @@ set(LINK_SCRIPT_BIN ${PROJECT_BINARY_DIR}/link_bin.ld)
 if (CONFIG_ARCH_ARM32)
 set(ARCH_INCLUDE include/arch/arm32)
 
-set(ARCH_START_ADDRESS "0x00020000")
-set(ARCH_SRAM_LENGTH "128K")
+set(ARCH_START_ADDRESS "${ARCH_BIN_START_ADDRESS}")
+set(ARCH_SRAM_LENGTH "${ARCH_BIN_SRAM_LENGTH}")
 
 configure_file(
     "${PROJECT_SOURCE_DIR}/link/arm32/link.ld"
     "${PROJECT_BINARY_DIR}/link_bin.ld"
 )
 
-set(ARCH_START_ADDRESS "0x00028000")
-set(ARCH_SRAM_LENGTH "100K")
+set(ARCH_START_ADDRESS "${ARCH_FEL_START_ADDRESS}")
+set(ARCH_SRAM_LENGTH "${ARCH_FEL_SRAM_LENGTH}")
 
 configure_file(
     "${PROJECT_SOURCE_DIR}/link/arm32/link.ld"
     "${PROJECT_BINARY_DIR}/link_elf.ld"
 )
+endif()
+
+# If the CONFIG_ARCH_ARM32 variable is defined, execute the following content
+if (CONFIG_ARCH_RISCV64)
+set(ARCH_INCLUDE include/arch/riscv64)
+
+set(ARCH_START_ADDRESS "${ARCH_BIN_START_ADDRESS}")
+set(ARCH_SRAM_LENGTH "${ARCH_BIN_SRAM_LENGTH}")
+
+configure_file(
+    "${PROJECT_SOURCE_DIR}/link/riscv64/link.ld"
+    "${PROJECT_BINARY_DIR}/link_bin.ld"
+)
+
+set(ARCH_START_ADDRESS "${ARCH_FEL_START_ADDRESS}")
+set(ARCH_SRAM_LENGTH "${ARCH_FEL_SRAM_LENGTH}")
 
+configure_file(
+    "${PROJECT_SOURCE_DIR}/link/riscv64/link.ld"
+    "${PROJECT_BINARY_DIR}/link_elf.ld"
+)
 endif()
 
 # Specify the paths of the include files

cmake/board/100ask-t113s3.cmake

@@ -31,3 +31,9 @@ endif()
 # Disable specific warning flags for C and C++ compilers
 set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers")
 set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast")
+
+set(ARCH_BIN_START_ADDRESS "0x00020000")
+set(ARCH_BIN_SRAM_LENGTH "128K")
+
+set(ARCH_FEL_START_ADDRESS "0x00028000")
+set(ARCH_FEL_SRAM_LENGTH "100K")

cmake/board/tinyvision.cmake

@@ -31,3 +31,9 @@ endif()
 # Disable specific warning flags for C and C++ compilers
 set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers")
 set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast")
+
+set(ARCH_BIN_START_ADDRESS "0x00020000")
+set(ARCH_BIN_SRAM_LENGTH "128K")
+
+set(ARCH_FEL_START_ADDRESS "0x00028000")
+set(ARCH_FEL_SRAM_LENGTH "100K")

cmake/board/yuzukilizard.cmake

@@ -31,3 +31,9 @@ endif()
 # Disable specific warning flags for C and C++ compilers
 set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers")
 set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast")
+
+set(ARCH_BIN_START_ADDRESS "0x00020000")
+set(ARCH_BIN_SRAM_LENGTH "128K")
+
+set(ARCH_FEL_START_ADDRESS "0x00028000")
+set(ARCH_FEL_SRAM_LENGTH "100K")

include/arch/riscv64/linkage.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef __RISCV64_LINKAGE_H__
+#define __RISCV64_LINKAGE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if __riscv_xlen == 64
+#define LREG ld
+#define SREG sd
+#define REGSZ 8
+#define RVPTR .dword
+#elif __riscv_xlen == 32
+#define LREG lw
+#define SREG sw
+#define REGSZ 4
+#define RVPTR .word
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RISCV64_LINKAGE_H__ */

src/arch/CMakeLists.txt

@@ -1,4 +1,8 @@
 
 if (CONFIG_ARCH_ARM32)
     add_subdirectory(arm32)
+endif()
+
+if (CONFIG_ARCH_RISCV64)
+    add_subdirectory(riscv64)
 endif()

src/arch/riscv64/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0 
+
+add_library(arch-obj OBJECT
+    timer.c
+)

src/arch/riscv64/memcpy.S

@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <linkage.h>
+
+	.global memcpy
+	.type memcpy, %function
+	.align 3
+memcpy:
+	move t6, a0
+	sltiu a3, a2, 128
+	bnez a3, 4f
+	andi a3, t6, REGSZ - 1
+	andi a4, a1, REGSZ - 1
+	bne a3, a4, 4f
+	beqz a3, 2f
+	andi a3, a1, ~(REGSZ - 1)
+	addi a3, a3, REGSZ
+	sub a4, a3, a1
+1:	lb a5, 0(a1)
+	addi a1, a1, 1
+	sb a5, 0(t6)
+	addi t6, t6, 1
+	bltu a1, a3, 1b
+	sub a2, a2, a4
+2:	andi a4, a2, ~((16 * REGSZ) - 1)
+	beqz a4, 4f
+	add a3, a1, a4
+3:	LREG a4,          0(a1)
+	LREG a5,      REGSZ(a1)
+	LREG a6,  2 * REGSZ(a1)
+	LREG a7,  3 * REGSZ(a1)
+	LREG t0,  4 * REGSZ(a1)
+	LREG t1,  5 * REGSZ(a1)
+	LREG t2,  6 * REGSZ(a1)
+	LREG t3,  7 * REGSZ(a1)
+	LREG t4,  8 * REGSZ(a1)
+	LREG t5,  9 * REGSZ(a1)
+	SREG a4,          0(t6)
+	SREG a5,      REGSZ(t6)
+	SREG a6,  2 * REGSZ(t6)
+	SREG a7,  3 * REGSZ(t6)
+	SREG t0,  4 * REGSZ(t6)
+	SREG t1,  5 * REGSZ(t6)
+	SREG t2,  6 * REGSZ(t6)
+	SREG t3,  7 * REGSZ(t6)
+	SREG t4,  8 * REGSZ(t6)
+	SREG t5,  9 * REGSZ(t6)
+	LREG a4, 10 * REGSZ(a1)
+	LREG a5, 11 * REGSZ(a1)
+	LREG a6, 12 * REGSZ(a1)
+	LREG a7, 13 * REGSZ(a1)
+	LREG t0, 14 * REGSZ(a1)
+	LREG t1, 15 * REGSZ(a1)
+	addi a1, a1, 16 * REGSZ
+	SREG a4, 10 * REGSZ(t6)
+	SREG a5, 11 * REGSZ(t6)
+	SREG a6, 12 * REGSZ(t6)
+	SREG a7, 13 * REGSZ(t6)
+	SREG t0, 14 * REGSZ(t6)
+	SREG t1, 15 * REGSZ(t6)
+	addi t6, t6, 16 * REGSZ
+	bltu a1, a3, 3b
+	andi a2, a2, (16 * REGSZ) - 1
+4:	beqz a2, 6f
+	add a3, a1, a2
+	or a5, a1, t6
+	or a5, a5, a3
+	andi a5, a5, 3
+	bnez a5, 5f
+7:	lw a4, 0(a1)
+	addi a1, a1, 4
+	sw a4, 0(t6)
+	addi t6, t6, 4
+	bltu a1, a3, 7b
+	ret
+5:	lb a4, 0(a1)
+	addi a1, a1, 1
+	sb a4, 0(t6)
+	addi t6, t6, 1
+	bltu a1, a3, 5b
+6:	ret

src/arch/riscv64/memset.S

@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <linkage.h>
+
+	.global memset
+	.type memset, %function
+	.align 3
+memset:
+	move t0, a0
+	sltiu a3, a2, 16
+	bnez a3, 4f
+	addi a3, t0, REGSZ - 1
+	andi a3, a3, ~(REGSZ - 1)
+	beq a3, t0, 2f
+	sub a4, a3, t0
+1:	sb a1, 0(t0)
+	addi t0, t0, 1
+	bltu t0, a3, 1b
+	sub a2, a2, a4
+2:	andi a1, a1, 0xff
+	slli a3, a1, 8
+	or a1, a3, a1
+	slli a3, a1, 16
+	or a1, a3, a1
+#if __riscv_xlen == 64
+	slli a3, a1, 32
+	or a1, a3, a1
+#endif
+	andi a4, a2, ~(REGSZ - 1)
+	add a3, t0, a4
+	andi a4, a4, 31 * REGSZ
+	beqz a4, 3f
+	neg a4, a4
+	addi a4, a4, 32 * REGSZ
+	sub t0, t0, a4
+	la a5, 3f
+#if __riscv_xlen == 64
+	srli a4, a4, 1
+#endif
+	add a5, a5, a4
+	jr a5
+3:	SREG a1,          0(t0)
+	SREG a1,      REGSZ(t0)
+	SREG a1,  2 * REGSZ(t0)
+	SREG a1,  3 * REGSZ(t0)
+	SREG a1,  4 * REGSZ(t0)
+	SREG a1,  5 * REGSZ(t0)
+	SREG a1,  6 * REGSZ(t0)
+	SREG a1,  7 * REGSZ(t0)
+	SREG a1,  8 * REGSZ(t0)
+	SREG a1,  9 * REGSZ(t0)
+	SREG a1, 10 * REGSZ(t0)
+	SREG a1, 11 * REGSZ(t0)
+	SREG a1, 12 * REGSZ(t0)
+	SREG a1, 13 * REGSZ(t0)
+	SREG a1, 14 * REGSZ(t0)
+	SREG a1, 15 * REGSZ(t0)
+	SREG a1, 16 * REGSZ(t0)
+	SREG a1, 17 * REGSZ(t0)
+	SREG a1, 18 * REGSZ(t0)
+	SREG a1, 19 * REGSZ(t0)
+	SREG a1, 20 * REGSZ(t0)
+	SREG a1, 21 * REGSZ(t0)
+	SREG a1, 22 * REGSZ(t0)
+	SREG a1, 23 * REGSZ(t0)
+	SREG a1, 24 * REGSZ(t0)
+	SREG a1, 25 * REGSZ(t0)
+	SREG a1, 26 * REGSZ(t0)
+	SREG a1, 27 * REGSZ(t0)
+	SREG a1, 28 * REGSZ(t0)
+	SREG a1, 29 * REGSZ(t0)
+	SREG a1, 30 * REGSZ(t0)
+	SREG a1, 31 * REGSZ(t0)
+	addi t0, t0, 32 * REGSZ
+	bltu t0, a3, 3b
+	andi a2, a2, REGSZ - 1
+4:	beqz a2, 6f
+	add a3, t0, a2
+5:	sb a1, 0(t0)
+	addi t0, t0, 1
+	bltu t0, a3, 5b
+6:	ret

src/arch/riscv64/timer.c

@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <io.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <types.h>
+
+#include <log.h>
+
+#include <timer.h>
+
+/*
+ * 64bit arch timer.CNTPCT
+ * Freq = 24000000Hz
+ */
+uint64_t get_arch_counter(void) {
+    uint64_t cnt = 0;
+
+    asm volatile("csrr %0, time\n"
+                 : "=r"(cnt)
+                 :
+                 : "memory");
+
+    return cnt;
+}
+
+/*
+ * get current time.(millisecond)
+ */
+uint32_t time_ms(void) {
+    return get_arch_counter() / 24000;
+}
+
+/*
+ * get current time.(microsecond)
+ */
+uint64_t time_us(void) {
+    return get_arch_counter() / (uint64_t) 24;
+}
+
+void udelay(uint64_t us) {
+    uint64_t now;
+
+    now = time_us();
+    while (time_us() - now < us) {
+    };
+}
+
+void mdelay(uint32_t ms) {
+    udelay(ms * 1000);
+    uint32_t now;
+
+    now = time_ms();
+    while (time_ms() - now < ms) {
+    };
+}
+
+void sdelay(uint32_t loops) {
+    asm volatile(
+            "mv t0, %0\n"// Move the 'loops' value to register t0
+            "1:\n"
+            "addi t0, t0, -1\n"// Decrement t0 by 1
+            "bnez t0, 1b\n"    // Branch back to label 1 if t0 is not zero
+            :                  // No output operands
+            : "r"(loops)       // Input operand: loops
+            : "t0"             // Clobbered registers: t0
+    );
+}