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Small fixes to slowfil_srl #1

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Small fixes to slowfil_srl #1

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7176a99
WIP
eddiehung Mar 21, 2019
6620332
Merge branch 'master' into eh
eddiehung Mar 21, 2019
ecaf12a
Fix spacing
eddiehung Mar 21, 2019
b2c7ebd
Revert changes, tidy up
eddiehung Mar 21, 2019
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10 changes: 5 additions & 5 deletions bench/cpp/slowfil_srl_tb.cpp
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
////////////////////////////////////////////////////////////////////////////////
//
// Filename: slowfil_tb.cpp
// Filename: slowfil_srl_tb.cpp
//
// Project: DSP Filtering Example Project
//
Expand Down Expand Up @@ -68,11 +68,11 @@ static int nextlg(int vl) {
return r;
}

class SLOWFIL_TB : public FILTERTB<Vslowfil_srl> {
class SLOWFIL_SRL_TB : public FILTERTB<Vslowfil_srl> {
public:
bool m_done;

SLOWFIL_TB(void) {
SLOWFIL_SRL_TB(void) {
IW(::IW);
TW(::TW);
OW(::OW);
Expand Down Expand Up @@ -107,11 +107,11 @@ class SLOWFIL_TB : public FILTERTB<Vslowfil_srl> {
}
};

SLOWFIL_TB *tb;
SLOWFIL_SRL_TB *tb;

int main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
tb = new SLOWFIL_TB();
tb = new SLOWFIL_SRL_TB();

const int64_t TAPVALUE = -(1<<(IW-1));
const int64_t IMPULSE = (1<<(IW-1))-1;
Expand Down
4 changes: 2 additions & 2 deletions rtl/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ genericfir: $(VDIRFB)/Vgenericfir__ALL.a
fastfir: $(VDIRFB)/Vfastfir__ALL.a
symfil: $(VDIRFB)/Vsymfil__ALL.a
slowfil: $(VDIRFB)/Vslowfil__ALL.a
slowfil: $(VDIRFB)/Vslowfil_srl__ALL.a
slowfil_srl: $(VDIRFB)/Vslowfil_srl__ALL.a
slowsymf: $(VDIRFB)/Vslowsymf__ALL.a
shalfband: $(VDIRFB)/Vshalfband__ALL.a
smplfir: $(VDIRFB)/Vsmplfir__ALL.a
Expand Down Expand Up @@ -85,7 +85,7 @@ $(VDIRFB)/Vslowfil__ALL.a: $(VDIRFB)/Vslowfil.mk
$(SUBMAKE) $(VDIRFB)/ -f Vslowfil.mk Vslowfil__ALL.a

$(VDIRFB)/Vslowfil_srl__ALL.a: $(VDIRFB)/Vslowfil_srl.mk
$(SUBMAKE) $(VDIRFB)/ -f Vslowfil.mk Vslowfil_srl__ALL.a
$(SUBMAKE) $(VDIRFB)/ -f Vslowfil_srl.mk Vslowfil_srl__ALL.a

$(VDIRFB)/Vslowsymf__ALL.a: $(VDIRFB)/Vslowsymf.mk
$(SUBMAKE) $(VDIRFB)/ -f Vslowsymf.mk Vslowsymf__ALL.a
Expand Down
45 changes: 17 additions & 28 deletions rtl/slowfil_srl.v
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,6 @@ module slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
reg [(TW-1):0] tapmem [0:(MEMSZ-1)]; // Coef memory
reg signed [(TW-1):0] tap; // Value read from coef memory

//reg [(LGNTAPS-1):0] dwidx, didx; // Data write and read indices
reg [(LGNTAPS-1):0] tidx; // Coefficient read index
reg [(IW-1):0] dsrl [0:(MEMSZ-1)]; // Data memory
reg signed [(IW-1):0] data; // Data value read from memory
Expand Down Expand Up @@ -135,24 +134,17 @@ module slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu

// Notice how this data writing section is *independent* of the reset,
// depending only upon new sample data.
//initial dwidx = 0;
//always @(posedge i_clk)
// if (i_ce)
// dwidx <= dwidx + 1'b1;
//always @(posedge i_clk)
// if (i_ce)
// dmem[dwidx] <= i_sample;
always @(posedge i_clk)
if (i_ce)
dsrl[0] <= i_sample;
generate
genvar i;
for (i = 1; i < MEMSZ; i=i+1) begin
always @(posedge i_clk)
if (i_ce)
dsrl[i] <= dsrl[i-1];
end
endgenerate
always @(posedge i_clk)
if (i_ce)
dsrl[0] <= i_sample;
generate
genvar i;
for (i = 1; i < MEMSZ; i=i+1) begin
always @(posedge i_clk)
if (i_ce)
dsrl[i] <= dsrl[i-1];
end
endgenerate

//
//
Expand Down Expand Up @@ -188,17 +180,14 @@ module slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
else
pre_acc_ce[2:1] <= pre_acc_ce[1:0];

//initial didx = 0;
initial tidx = 0;
always @(posedge i_clk)
if (i_ce)
begin
//didx <= dwidx;
tidx <= 0;
end else begin
//didx <= didx - 1'b1;
tidx <= tidx + 1'b1;
end
if (i_ce)
begin
tidx <= 0;
end else begin
tidx <= tidx + 1'b1;
end

// m_ce is valid when the first index is valid
initial m_ce = 1'b0;
Expand Down