Open-Source SystemVerilog Development Environment for 1BitSquared IceBreaker FPGA
- Based on the Lattice Ice40UP5
- NOTE: included pcf file is for IceBreaker 1.0e
NOTE: LAST UPDATED JANUARY 2025
| Name | Description |
|---|---|
| Yosys | Verilog IEEE 1364-2005 Synthesis |
| NextPnR | FPGA Place-and-Route |
| Project IceStorm | Yosys/NextPnR compatibility layer for Lattice Ice40 FPGA architectures |
| Icarus Verilog | Verilog IEEE 1364-2005 Compiler and Simulator |
| Verilator | SystemVerilog Simulator |
| Verible | Formatting and Linting Tools for SystemVerilog |
| slang | SystemVerilog IEEE 1800-2023 Pre-Processor, acts as a plugin for Yosys |
| sv2v | SystemVerilog IEEE 1800-2017 to Verilog IEEE 1364-2005 conversion tool |
| Surfer | Waveform Viewer |
| CTags | Source Code Indexer |
| fd | WINDOWS ONLY - replacement for unix 'find' tool |
** Many of these tools are packaged in the YosysHQ OSS CAD Suite **
| Name | Description |
|---|---|
| src/ | Contains RTL for synthesis |
| test/ | Stores RTL testbench files |
| Makefile | Scripting to automate Simulation, Synthesis, Place and Route, and Programming |
| .rules.verible* | Instructions for automated linting, taken from this template |
| icebreaker.pcf | Pin definitions for the IceBreaker 1.0e |
Place in .git/hooks/*
| Hook | Description |
|---|---|
| pre-commit | Runs verilog linter checks and reformatting tools |
| post-commit | Regenerates tag file |
Example .gitignore
*verible*
tags
sv2v/*
build/*
sim/*