Mixed-signal-RISCV-based-SoC

Aim: To integrate rvmyth with a PLL (Phase Locked Loop) as a clock multiplier using open-source EDA tools. The whole project focuses on Mixed Signal Physical Design.

Block design of RVMYTH + PLL

RVMYTH - RISC V Core, test program is loaded into instruction memory.
avsdpll_1v8: PLL designed by VSD works as a multiplier (output_freq = x.input_freq). Depends on the drive strength of the buffers used in designing the PLL.
Generated output frequency is connected to the CLK pin of the processor. The functionality of the setup is tested using RTL and FPGA flows.

Tools used

• Makerchip is a free web-based IDE as well as available as makerchip-app, a virtual desktop application for developing high-quality integrated circuits.
• Icarus Verilog is a Verilog simulation and synthesis tool.
• GTKWave is a waveform viewer.
• Xilinx Vivado provides complete SoC-strength, IP-centric and system-centric, next generation development environment. Currently, this project is done using Vivado HL Design Edition 2019.1.

RTL flow

Steps to convert TL-Verilog to Verilog/System Verilog

pip3 install sandpiper-saas
sandpiper-saas -i design.tlv -o design.sv --iArgs

Steps for RTL Simulation of RVMYTH+PLL using iverilog

iverilog rvmyth_pll_tb.v rvmyth_pll.v clk_gate.v
./a.out
gtkwave rvmyth_pll.vcd

out[7:0]runs from 0-255, 255-0 and so on.

out(analog format) has peak value of 255.

FPGA flow

Note: Here, PLL from Xilinx Vivado is used. It converts input frequency of 33 MHz to 100MHz.
FPGA board used - Zedboard Zynq-7000 ARM/FPGA SoC Development Board

FPGA-RTL Simulation

FPGA Implementation and timing analysis

Observation: Faced hold violation in false path


False path has been indicated with red. Add false path constraint in vivado to ignore them.

Modify constraints.xdc -

set_false_path -hold -from [get_pins uut1/inst/plle2_adv_inst/CLKOUT0] -to [get_pins uut3/inst/ila_core_inst/*/D]
set_false_path -hold -from [get_pins uut1/inst/plle2_adv_inst/CLKOUT0] -to [get_pins uut3/inst/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[2].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/*/D]

Schematic