I am a VLSI enthusiast with a passion for chip design, RTL development, and digital logic. I believe that great hardware starts with strong fundamentals and precise design.
- Current Focus: Verilog, SystemVerilog, and ASIC design
- Learning: Physical Design and Timing Closure
- Interests: EDA tools, FPGA prototyping, and silicon optimization
- Expertise: Digital design, CMOS logic, and chip architecture
Hardware Design: Verilog | SystemVerilog | VHDL
EDA Tools: Cadence | Synopsys | ModelSim | Xilinx | Vivado
Programming: Python | C | Shell
Domains: RTL | FPGA | ASIC | Verification
“Every transistor counts — precision is the art of chip design.”