Web FPGA Simulator (Team 7)

🚀 Project Overview

This project aims to develop a web-based interface for an FPGA simulator. The interface will allow users (students and teachers) to visualize signal propagation inside an FPGA.

📚 Documents

• Functional Specifications
• Technical Specifications
• Project Charter
• Test Plan
• Test Cases
• User Manual

🔹 Key Features

• 2D Visualization of BELs and signal routing in the FPGA
• Real-time simulation with adjustable speed controls (x1, x2, x4…)
• Preloaded Verilog Applications for educational use
• Teacher Dashboard to upload Verilog files and testbenches
• Integration with Impulse and ModelSim for simulation

👤 Our Team

Team Members

Photo	Name	Role	Links
	Pierre GORIN	Project Manager	LinkedIn GitHub
	Aurélien FERNANDEZ	Program Manager	LinkedIn GitHub
	Abderrazaq MAKRAN	Technical Lead	LinkedIn GitHub
	Guillaume DERAMCHI	Quality Assurance	LinkedIn GitHub
	Enzo GUILLOUCHE	Software Engineer 1	LinkedIn GitHub
	Antoine PREVOST	Software Engineer 2	LinkedIn GitHub
	Max BERNARD	Technical Writer	LinkedIn GitHub

🛠 Technologies Used

Backend

• NanoXplore Impulse
• ModelSim

Frontend

• To be decided

Other Tools

• Trello for project management
• GitHub for version control
• Slack for communication

📂 Project Structure

.
├── Code
│   ├── Backend
│   └── Frontend
├── Documents
│   ├── FunctionalSpecifications
│   │   ├── FunctionalSpecifications.md
│   │   └── img
│   │       └── placeholder.png
│   ├── Management
│   │   ├── BestPractices.md
│   │   ├── ProjectCharter.md
│   │   └── img
│   ├── QA
│   │   ├── TestCases.md
│   │   ├── TestPlan.md
│   │   └── img
│   ├── TechnicalSpecifications
│   │   ├── TechnicalSpecifications.md
│   │   └── img
│   └── UserManual
│       ├── UserManual.md
│       └── img
├── LICENSE.md
├── README.md
└── Scripts