FPGA

This repository includes all the lab projects and computer assignment of the FPGA-Based Embedded Design course - Fall 2021
This repository contains one computer assignment and four lab projects.

CA1: Design and Implementation of FIR filter in Verilog

In this assignment, an FIR filter was design in Verilog hardware description language and synthesized in Quartus on a Cyclon II series FPGA model and evaluated its speed and resource consumption. Also, I tried to determine the best settings to have a good balance between computation speed and resource (AKA area) consumption. All the adjusted settings results are available in the report file.