all blocks with active low reset

the IP blocks used in this example were updated to use only active low reset. the inverters used in the reset and in the clock in the previous version were removed. The readme was improved.

1st version working in the fpga

this version has two DMA test apps that send packet to the NoC via DMA. The DMA send data which passes trough two routers and finally reaches the slave port of the DMA, reaching again the ARM processor. The router L_m port includes the AXI streaming LAST signal to communicate with the slave DMA interface.

Just clone it, plug the board, run the build.sh and you are ready to go !

initial version

This is a partially functional project to test the integration of Zynq and the Hermes NoC router. The PL subsystem is initially target to only 10MHz since there are few complex paths in Hermes, in the first signal inside the buffer. The DMA driver is also very simplified since it only sends a packet from zynq to the router. The receiving port turns on a LED in the zedboard. The positive aspect is that now the design is fully integrated to git, so i can get a better control over its evolution and history.
Next steps:

• better driver sending ans received several packets with different sizes and timing
• better test design, perhaps connecting two routers such that it would allow loopback testing